[PATCH] D24625: [DAG] Remove isVectorClearMaskLegal() check from vector_build dagcombine

[Michael Kuperstein via llvm-commits]

mkuper created this revision.
mkuper added reviewers: arsenm, tstellarAMD, uweigand, t.p.northover, hfinkel.
mkuper added a subscriber: llvm-commits.
Herald added subscribers: nhaehnle, wdng, samparker, rengolin, aemerson.

This check currently doesn't seem to do anything useful on any in-tree target, and I don't think it makes sense to keep it:
On non-x86, it always evaluates to false, so we never hit the code path that creates the shuffle with zero.
On x86, it just forwards to isShuffleMaskLegal().

It's possible we should be checking isShuffleMaskLegal() for all the shuffles we generate here, but (a) that should not be x86-specific, and (b) I don't see any reason for it to be specific to shuffles with zero.

(Not deleting isVectorClearMaskLegal() itself, since there's one more DAGCombine that uses it.)

https://reviews.llvm.org/D24625

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AMDGPU/r600-export-fix.ll
  test/CodeGen/SystemZ/vec-perm-13.ll

Index: test/CodeGen/SystemZ/vec-perm-13.ll
===================================================================
--- test/CodeGen/SystemZ/vec-perm-13.ll
+++ test/CodeGen/SystemZ/vec-perm-13.ll
@@ -19,8 +19,8 @@
 ; CHECK-VECTOR-NEXT: .space  1                                        
 ; CHECK-VECTOR-NEXT: .byte   6
 ; CHECK-VECTOR-NEXT: .byte   7
-; CHECK-VECTOR-NEXT: .byte   16
-; CHECK-VECTOR-NEXT: .byte   17
+; CHECK-VECTOR-NEXT: .byte   22
+; CHECK-VECTOR-NEXT: .byte   23
 ; CHECK-VECTOR-NEXT: .space  1                                        
 ; CHECK-VECTOR-NEXT: .space  1                                        
 ; CHECK-VECTOR-NEXT: .space  1                                        
Index: test/CodeGen/AMDGPU/r600-export-fix.ll
===================================================================
--- test/CodeGen/AMDGPU/r600-export-fix.ll
+++ test/CodeGen/AMDGPU/r600-export-fix.ll
@@ -3,9 +3,9 @@
 ;CHECK:	EXPORT T{{[0-9]}}.XYZW
 ;CHECK:	EXPORT T{{[0-9]}}.0000
 ;CHECK: EXPORT T{{[0-9]}}.0000
-;CHECK: EXPORT T{{[0-9]}}.0XYZ
+;CHECK: EXPORT T{{[0-9]}}.0YZW
 ;CHECK: EXPORT T{{[0-9]}}.XYZW
-;CHECK: EXPORT T{{[0-9]}}.YZ00
+;CHECK: EXPORT T{{[0-9]}}.XY00
 ;CHECK: EXPORT T{{[0-9]}}.0000
 ;CHECK: EXPORT T{{[0-9]}}.0000
 
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13064,13 +13064,6 @@
     Mask[i] = Vec2Offset + ExtIndex;
   }
 
-  // Avoid introducing illegal shuffles with zero.
-  // TODO: This doesn't actually do anything smart at the moment.
-  // We should either delete this, or check legality for all the shuffles
-  // we create.
-  if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
-    return SDValue();
-
   // The type the input vectors may have changed above.
   InVT1 = VecIn1.getValueType();
 


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