[llvm] r281630 - [InstCombine] add vector tests for icmp (sub nsw)
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 15 10:54:48 PDT 2016
Author: spatel
Date: Thu Sep 15 12:54:47 2016
New Revision: 281630
URL: http://llvm.org/viewvc/llvm-project?rev=281630&view=rev
Log:
[InstCombine] add vector tests for icmp (sub nsw)
Modified:
llvm/trunk/test/Transforms/InstCombine/icmp.ll
Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=281630&r1=281629&r2=281630&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Thu Sep 15 12:54:47 2016
@@ -2313,6 +2313,17 @@ define i1 @f1(i64 %a, i64 %b) {
ret i1 %v
}
+define <2 x i1> @f1_vec(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @f1_vec(
+; CHECK-NEXT: [[T:%.*]] = sub nsw <2 x i64> %a, %b
+; CHECK-NEXT: [[V:%.*]] = icmp sgt <2 x i64> [[T]], <i64 -1, i64 -1>
+; CHECK-NEXT: ret <2 x i1> [[V]]
+;
+ %t = sub nsw <2 x i64> %a, %b
+ %v = icmp sgt <2 x i64> %t, <i64 -1, i64 -1>
+ ret <2 x i1> %v
+}
+
define i1 @f2(i64 %a, i64 %b) {
; CHECK-LABEL: @f2(
; CHECK-NEXT: [[V:%.*]] = icmp sgt i64 %a, %b
@@ -2323,6 +2334,17 @@ define i1 @f2(i64 %a, i64 %b) {
ret i1 %v
}
+define <2 x i1> @f2_vec(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @f2_vec(
+; CHECK-NEXT: [[T:%.*]] = sub nsw <2 x i64> %a, %b
+; CHECK-NEXT: [[V:%.*]] = icmp sgt <2 x i64> [[T]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[V]]
+;
+ %t = sub nsw <2 x i64> %a, %b
+ %v = icmp sgt <2 x i64> %t, zeroinitializer
+ ret <2 x i1> %v
+}
+
define i1 @f3(i64 %a, i64 %b) {
; CHECK-LABEL: @f3(
; CHECK-NEXT: [[V:%.*]] = icmp slt i64 %a, %b
@@ -2333,6 +2355,17 @@ define i1 @f3(i64 %a, i64 %b) {
ret i1 %v
}
+define <2 x i1> @f3_vec(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @f3_vec(
+; CHECK-NEXT: [[T:%.*]] = sub nsw <2 x i64> %a, %b
+; CHECK-NEXT: [[V:%.*]] = icmp slt <2 x i64> [[T]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[V]]
+;
+ %t = sub nsw <2 x i64> %a, %b
+ %v = icmp slt <2 x i64> %t, zeroinitializer
+ ret <2 x i1> %v
+}
+
define i1 @f4(i64 %a, i64 %b) {
; CHECK-LABEL: @f4(
; CHECK-NEXT: [[V:%.*]] = icmp sle i64 %a, %b
@@ -2343,6 +2376,17 @@ define i1 @f4(i64 %a, i64 %b) {
ret i1 %v
}
+define <2 x i1> @f4_vec(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @f4_vec(
+; CHECK-NEXT: [[T:%.*]] = sub nsw <2 x i64> %a, %b
+; CHECK-NEXT: [[V:%.*]] = icmp slt <2 x i64> [[T]], <i64 1, i64 1>
+; CHECK-NEXT: ret <2 x i1> [[V]]
+;
+ %t = sub nsw <2 x i64> %a, %b
+ %v = icmp slt <2 x i64> %t, <i64 1, i64 1>
+ ret <2 x i1> %v
+}
+
define i32 @f5(i8 %a, i8 %b) {
; CHECK-LABEL: @f5(
; CHECK-NEXT: [[CONV:%.*]] = zext i8 %a to i32
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