[PATCH] D24521: [ARM] Add Marvell PJ4 cpu
Kai Nacke via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 13 13:25:52 PDT 2016
Kai created this revision.
Kai added a reviewer: rengolin.
Kai added a subscriber: llvm-commits.
Herald added subscribers: samparker, rengolin, aemerson.
The Marvell PJ4 cpus are ARMv7 compliant cpus similar to Cortex-A8 but based on a custom design.
This patch adds basic support for the PJ4 cpus. Details can be found in the Linux kernel README https://www.kernel.org/doc/readme/Documentation-arm-Marvell-README.
https://reviews.llvm.org/D24521
Files:
lib/Support/Host.cpp
lib/Target/ARM/ARM.td
lib/Target/ARM/ARMSubtarget.cpp
lib/Target/ARM/ARMSubtarget.h
Index: lib/Target/ARM/ARMSubtarget.h
===================================================================
--- lib/Target/ARM/ARMSubtarget.h
+++ lib/Target/ARM/ARMSubtarget.h
@@ -45,7 +45,7 @@
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3,
CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,
- Krait, Swift, ExynosM1
+ Krait, Swift, ExynosM1, MarvellPJ4
};
enum ARMProcClassEnum {
None, AClass, RClass, MClass
Index: lib/Target/ARM/ARMSubtarget.cpp
===================================================================
--- lib/Target/ARM/ARMSubtarget.cpp
+++ lib/Target/ARM/ARMSubtarget.cpp
@@ -239,6 +239,7 @@
case CortexR7:
case CortexM3:
case ExynosM1:
+ case MarvellPJ4:
break;
case Krait:
PreISelOperandLatencyAdjustment = 1;
Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -344,6 +344,9 @@
def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
"Swift ARM processors", []>;
+def ProcMarvellPJ4 : SubtargetFeature<"marvellpj4", "ARMProcFamily", "MarvellPJ4",
+ "Marvell PJ4 processors", []>;
+
def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
"Samsung Exynos-M1 processors", []>;
@@ -792,6 +795,13 @@
FeatureCrypto,
FeatureZCZeroing]>;
+def : ProcNoItin<"marvell-pj4", [HasV7Ops, ProcMarvellPJ4,
+ FeatureVFP3,
+ FeatureFP16,
+ FeatureDSP,
+ FeatureHWDiv,
+ FeatureThumb2]>;
+
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
FeatureHWDiv,
FeatureHWDivARM,
Index: lib/Support/Host.cpp
===================================================================
--- lib/Support/Host.cpp
+++ lib/Support/Host.cpp
@@ -1093,6 +1093,25 @@
.Case("0x06f", "krait") // APQ8064
.Default("generic");
+ if (Implementer == "0x56") { // Marvell Technology Group Ltd.
+ // Look for the CPU architecture line.
+ for (unsigned I = 0, E = Lines.size(); I != E; ++I)
+ if (Lines[I].startswith("CPU architecture"))
+ // Architecture must be ARMv7.
+ if (Lines[I].substr(16).ltrim("\t :") != "7")
+ return "generic";
+ // Look for the CPU part line.
+ for (unsigned I = 0, E = Lines.size(); I != E; ++I)
+ if (Lines[I].startswith("CPU part"))
+ // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
+ // values correspond to the "Part number" in the CP15/c0 register. The
+ // contents are specified in the various processor manuals.
+ return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
+ .Case("0x581", "marvell-pj4") // Sheeva PJ4 / PJ4B
+ .Case("0x584", "marvell-pj4") // Sheeva PJ4B-MP / PJ4C
+ .Default("generic");
+ }
+
return "generic";
}
#elif defined(__linux__) && defined(__s390x__)
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