[llvm] r281362 - [DAGCombiner] Use APInt directly in (shl (zext (srl x, C)), C) combine range test

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Sep 13 13:33:29 2016
New Revision: 281362

URL: http://llvm.org/viewvc/llvm-project?rev=281362&view=rev
Log:
[DAGCombiner] Use APInt directly in (shl (zext (srl x, C)), C) combine range test

To avoid assertion, we must ensure that the inner shift constant is within range before calling ConstantSDNode::getZExtValue(). We already know that the outer shift constant is in range.

Followup to D23007

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/shift-i128.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=281362&r1=281361&r2=281362&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 13 13:33:29 2016
@@ -4545,8 +4545,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N)
       N0.getOperand(0).getOpcode() == ISD::SRL) {
     SDValue N0Op0 = N0.getOperand(0);
     if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
-      uint64_t c1 = N0Op0C1->getZExtValue();
-      if (c1 < VT.getScalarSizeInBits()) {
+      if (N0Op0C1->getAPIntValue().ult(VT.getScalarSizeInBits())) {
+        uint64_t c1 = N0Op0C1->getZExtValue();
         uint64_t c2 = N1C->getZExtValue();
         if (c1 == c2) {
           SDValue NewOp0 = N0.getOperand(0);

Modified: llvm/trunk/test/CodeGen/X86/shift-i128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-i128.ll?rev=281362&r1=281361&r2=281362&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-i128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-i128.ll Tue Sep 13 13:33:29 2016
@@ -134,3 +134,10 @@ define <2 x i256> @shl_zext_shl_outofran
   %3 = shl <2 x i256> %2, <i256 128, i256 128>
   ret <2 x i256> %3
 }
+
+define <2 x i256> @shl_zext_lshr_outofrange(<2 x i128> %a0) {
+  %1 = lshr <2 x i128> %a0, <i128 -1, i128 -1>
+  %2 = zext <2 x i128> %1 to <2 x i256>
+  %3 = shl <2 x i256> %2, <i256 128, i256 128>
+  ret <2 x i256> %3
+}