[llvm] r281306 - Revert of r281304 as it is causing build bot failures in hexagon
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 13 01:51:59 PDT 2016
Author: sjoerdmeijer
Date: Tue Sep 13 03:51:59 2016
New Revision: 281306
URL: http://llvm.org/viewvc/llvm-project?rev=281306&view=rev
Log:
Revert of r281304 as it is causing build bot failures in hexagon
hwloop regression tests. These tests pass locally; will be investigating
where these differences come from.
Modified:
llvm/trunk/include/llvm/MC/MCInstrDesc.h
llvm/trunk/include/llvm/Target/Target.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original)
+++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Tue Sep 13 03:51:59 2016
@@ -124,7 +124,6 @@ enum Flag {
Pseudo,
Return,
Call,
- Add,
Barrier,
Terminator,
Branch,
@@ -235,9 +234,6 @@ public:
/// \brief Return true if the instruction is a return.
bool isReturn() const { return Flags & (1ULL << MCID::Return); }
- /// \brief Return true if the instruction is an add instruction.
- bool isAdd() const { return Flags & (1ULL << MCID::Add); }
-
/// \brief Return true if the instruction is a call.
bool isCall() const { return Flags & (1ULL << MCID::Call); }
Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Tue Sep 13 03:51:59 2016
@@ -371,7 +371,6 @@ class Instruction {
bit isSelect = 0; // Is this instruction a select instruction?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
- bit isAdd = 0; // Is this instruction an add instruction?
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
bit mayLoad = ?; // Is it possible for this inst to read memory?
bit mayStore = ?; // Is it possible for this inst to write memory?
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep 13 03:51:59 2016
@@ -3498,7 +3498,6 @@ def UBFX : I<(outs GPRnopc:$Rd),
// Arithmetic Instructions.
//
-let isAdd = 1 in
defm ADD : AsI1_bin_irs<0b0100, "add",
IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>;
defm SUB : AsI1_bin_irs<0b0010, "sub",
@@ -3514,11 +3513,9 @@ defm SUB : AsI1_bin_irs<0b0010, "sub",
// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
// support for an optional CPSR definition that corresponds to the DAG
// node's second value. We can then eliminate the implicit def of CPSR.
-let isAdd = 1 in
defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>;
defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
-let isAdd = 1 in
defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>;
defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Sep 13 03:51:59 2016
@@ -904,51 +904,49 @@ class T1sItGenEncodeImm<bits<5> opA, dag
let Inst{7-0} = imm8;
}
-let isAdd = 1 in {
- // Add with carry register
- let isCommutable = 1, Uses = [CPSR] in
- def tADC : // A8.6.2
- T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
- "adc", "\t$Rdn, $Rm",
- [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
-
- // Add immediate
- def tADDi3 : // A8.6.4 T1
- T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
- IIC_iALUi,
- "add", "\t$Rd, $Rm, $imm3",
- [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
- Sched<[WriteALU]> {
- bits<3> imm3;
- let Inst{8-6} = imm3;
- }
-
- def tADDi8 : // A8.6.4 T2
- T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
- (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
- "add", "\t$Rdn, $imm8",
- [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
- Sched<[WriteALU]>;
-
- // Add register
- let isCommutable = 1 in
- def tADDrr : // A8.6.6 T1
- T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
- IIC_iALUr,
- "add", "\t$Rd, $Rn, $Rm",
- [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
-
- let hasSideEffects = 0 in
- def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
- "add", "\t$Rdn, $Rm", []>,
- T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
- // A8.6.6 T2
- bits<4> Rdn;
- bits<4> Rm;
- let Inst{7} = Rdn{3};
- let Inst{6-3} = Rm;
- let Inst{2-0} = Rdn{2-0};
- }
+// Add with carry register
+let isCommutable = 1, Uses = [CPSR] in
+def tADC : // A8.6.2
+ T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
+ "adc", "\t$Rdn, $Rm",
+ [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+
+// Add immediate
+def tADDi3 : // A8.6.4 T1
+ T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
+ IIC_iALUi,
+ "add", "\t$Rd, $Rm, $imm3",
+ [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
+ Sched<[WriteALU]> {
+ bits<3> imm3;
+ let Inst{8-6} = imm3;
+}
+
+def tADDi8 : // A8.6.4 T2
+ T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
+ (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
+ "add", "\t$Rdn, $imm8",
+ [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
+ Sched<[WriteALU]>;
+
+// Add register
+let isCommutable = 1 in
+def tADDrr : // A8.6.6 T1
+ T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
+ IIC_iALUr,
+ "add", "\t$Rd, $Rn, $Rm",
+ [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+
+let hasSideEffects = 0 in
+def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
+ "add", "\t$Rdn, $Rm", []>,
+ T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
+ // A8.6.6 T2
+ bits<4> Rdn;
+ bits<4> Rm;
+ let Inst{7} = Rdn{3};
+ let Inst{6-3} = Rm;
+ let Inst{2-0} = Rdn{2-0};
}
// AND register
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep 13 03:51:59 2016
@@ -2038,7 +2038,6 @@ def : Thumb2ExtractPat<(add rGPR:$Rn, (a
// Arithmetic Instructions.
//
-let isAdd = 1 in
defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Tue Sep 13 03:51:59 2016
@@ -411,8 +411,10 @@ bool HexagonHardwareLoops::findInduction
unsigned PhiOpReg = Phi->getOperand(i).getReg();
MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
+ unsigned UpdOpc = DI->getOpcode();
+ bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp);
- if (DI->getDesc().isAdd()) {
+ if (isAdd) {
// If the register operand to the add is the PHI we're looking at, this
// meets the induction pattern.
unsigned IndReg = DI->getOperand(1).getReg();
@@ -1590,8 +1592,10 @@ bool HexagonHardwareLoops::fixupInductio
unsigned PhiReg = Phi->getOperand(i).getReg();
MachineInstr *DI = MRI->getVRegDef(PhiReg);
+ unsigned UpdOpc = DI->getOpcode();
+ bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp);
- if (DI->getDesc().isAdd()) {
+ if (isAdd) {
// If the register operand to the add/sub is the PHI we are looking
// at, this meets the induction pattern.
unsigned IndReg = DI->getOperand(1).getReg();
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Sep 13 03:51:59 2016
@@ -406,7 +406,7 @@ multiclass Addri_Pred<string mnemonic, b
let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
multiclass Addri_base<string mnemonic, SDNode OpNode> {
let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
- let opExtendable = 2, opExtentBits = 16, isPredicable = 1, isAdd = 1 in
+ let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
def A2_#NAME : T_Addri<s16Ext>;
let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
@@ -1292,7 +1292,6 @@ class T_ALU64_arith<string mnemonic, bit
: T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
IsComm, "">;
-let isAdd = 1 in
def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
Modified: llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll Tue Sep 13 03:51:59 2016
@@ -4,16 +4,36 @@
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon-unknown-none"
+%struct.aDataType = type { i16, i16, i16, i16, i16, i16*, i16*, i16*, i8*, i16*, i16*, i16*, i8* }
-define i32 @foo(i16 %a, i32 %b) #0 {
- %and = and i16 %a, -4
+define i8* @a_get_score(%struct.aDataType* nocapture %pData, i16 signext %gmmModelIndex, i16* nocapture %pGmmScoreL16Q4) #0 {
+entry:
+ %numSubVector = getelementptr inbounds %struct.aDataType, %struct.aDataType* %pData, i32 0, i32 3
+ %0 = load i16, i16* %numSubVector, align 2, !tbaa !0
+ %and = and i16 %0, -4
+ %b = getelementptr inbounds %struct.aDataType, %struct.aDataType* %pData, i32 0, i32 8
+ %1 = load i8*, i8** %b, align 4, !tbaa !3
%conv3 = sext i16 %and to i32
- %add13 = mul i32 %b, 65536
+ %cmp21 = icmp sgt i16 %and, 0
+ br i1 %cmp21, label %for.inc.preheader, label %for.end
+
+for.inc.preheader: ; preds = %entry
+ br label %for.inc
+
+for.inc: ; preds = %for.inc.preheader, %for.inc
+ %j.022 = phi i32 [ %phitmp, %for.inc ], [ 0, %for.inc.preheader ]
+ %add13 = mul i32 %j.022, 65536
%sext = add i32 %add13, 262144
%phitmp = ashr exact i32 %sext, 16
- ret i32 %phitmp
-}
+ %cmp = icmp slt i32 %phitmp, %conv3
+ br i1 %cmp, label %for.inc, label %for.end.loopexit
+for.end.loopexit: ; preds = %for.inc
+ br label %for.end
+
+for.end: ; preds = %for.end.loopexit, %entry
+ ret i8* %1
+}
attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Tue Sep 13 03:51:59 2016
@@ -230,7 +230,6 @@ template <typename T> class ArrayRef;
bool isSelect : 1;
bool isBarrier : 1;
bool isCall : 1;
- bool isAdd : 1;
bool canFoldAsLoad : 1;
bool mayLoad : 1;
bool mayLoad_Unset : 1;
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=281306&r1=281305&r2=281306&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Tue Sep 13 03:51:59 2016
@@ -482,7 +482,6 @@ void InstrInfoEmitter::emitRecord(const
if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)";
if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)";
if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)";
- if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)";
if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)";
if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)";
if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)";
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