[llvm] r281216 - [AMDGPU] Assembler: Move disabled SDWA and DPP instruction into Disable asm variant

[Sam Kolton via llvm-commits]

Author: skolton
Date: Mon Sep 12 09:42:43 2016
New Revision: 281216

URL: http://llvm.org/viewvc/llvm-project?rev=281216&view=rev
Log:
[AMDGPU] Assembler: Move disabled SDWA and DPP instruction into Disable asm variant

Summary: This removes disabled instructions from match tables so we will not match them at all.

Reviewers: tstellarAMD, vpykhtin, artem.tamazov

Subscribers: wdng, nhaehnle, arsenm

Differential Revision: https://reviews.llvm.org/D24452

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=281216&r1=281215&r2=281216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td Mon Sep 12 09:42:43 2016
@@ -358,6 +358,8 @@ def AMDGPUAsmVariants {
   int SDWA_ID = 2;
   string DPP = "DPP";
   int DPP_ID = 3;
+  string Disable = "Disable";
+  int Disable_ID = 4;
 }
 
 def DefaultAMDGPUAsmParserVariant : AsmParserVariant {

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=281216&r1=281215&r2=281216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Mon Sep 12 09:42:43 2016
@@ -1245,6 +1245,8 @@ class VOP1_DPP <vop1 op, string opName,
   VOP1_DPPe <op.VI>,
   VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> {
   let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
+  let AsmVariantName = !if(p.HasExt, AMDGPUAsmVariants.DPP,
+                                     AMDGPUAsmVariants.Disable);
   let DecoderNamespace = "DPP";
   let DisableDecoder = DisableVIDecoder;
   let src0_modifiers = !if(p.HasModifiers, ?, 0);
@@ -1280,6 +1282,8 @@ class VOP1_SDWA <vop1 op, string opName,
   SDWADisableFields <p> {
   let AsmMatchConverter = "cvtSdwaVOP1";
   let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
+  let AsmVariantName = !if(p.HasExt, AMDGPUAsmVariants.SDWA,
+                                     AMDGPUAsmVariants.Disable);
   let DecoderNamespace = "SDWA";
   let DisableDecoder = DisableVIDecoder;
 }
@@ -1342,6 +1346,8 @@ class VOP2_DPP <vop2 op, string opName,
   VOP2_DPPe <op.VI>,
   VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> {
   let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
+  let AsmVariantName = !if(p.HasExt, AMDGPUAsmVariants.DPP,
+                                     AMDGPUAsmVariants.Disable);
   let DecoderNamespace = "DPP";
   let DisableDecoder = DisableVIDecoder;
   let src0_modifiers = !if(p.HasModifiers, ?, 0);
@@ -1354,6 +1360,8 @@ class VOP2_SDWA <vop2 op, string opName,
   SDWADisableFields <p> {
   let AsmMatchConverter = "cvtSdwaVOP2";
   let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
+  let AsmVariantName = !if(p.HasExt, AMDGPUAsmVariants.SDWA,
+                                     AMDGPUAsmVariants.Disable);
   let DecoderNamespace = "SDWA";
   let DisableDecoder = DisableVIDecoder;
 }
@@ -1809,6 +1817,8 @@ class VOPC_SDWA <vopc op, string opName,
   let hasSideEffects = DefExec;
   let AsmMatchConverter = "cvtSdwaVOPC";
   let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
+  let AsmVariantName = !if(p.HasExt, AMDGPUAsmVariants.SDWA,
+                                     AMDGPUAsmVariants.Disable);
   let DecoderNamespace = "SDWA";
   let DisableDecoder = DisableVIDecoder;
 }