[llvm] r281127 - AMDGPU: Fix scheduling info for spill pseudos

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Fri Sep  9 20:20:28 2016
New Revision: 281127

URL: http://llvm.org/viewvc/llvm-project?rev=281127&view=rev
Log:
AMDGPU: Fix scheduling info for spill pseudos

These defaulted to Write32Bit. I don't think this actually matters
since these don't exist during scheduling.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=281127&r1=281126&r2=281127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Fri Sep  9 20:20:28 2016
@@ -1365,7 +1365,8 @@ defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg
 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
 
 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
-  let UseNamedOperandTable = 1, VGPRSpill = 1 in {
+  let UseNamedOperandTable = 1, VGPRSpill = 1,
+       SchedRW = [WriteVMEM] in {
     def _SAVE : VPseudoInstSI <
       (outs),
       (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
@@ -1386,7 +1387,7 @@ multiclass SI_SPILL_VGPR <RegisterClass
       // (2 * 4) + (8 * num_subregs) bytes maximum
       let Size = !add(!shl(!srl(vgpr_class.Size, 5), 3), 8);
     }
-  } // End UseNamedOperandTable = 1, VGPRSpill = 1
+  } // End UseNamedOperandTable = 1, VGPRSpill = 1, SchedRW = [WriteVMEM]
 }
 
 defm SI_SPILL_V32  : SI_SPILL_VGPR <VGPR_32>;