[llvm] r281125 - [CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantLoad. NFC
Justin Lebar via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 9 18:03:21 PDT 2016
Author: jlebar
Date: Fri Sep 9 20:03:20 2016
New Revision: 281125
URL: http://llvm.org/viewvc/llvm-project?rev=281125&view=rev
Log:
[CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantLoad. NFC
Summary:
I want to separate out the notions of invariance and dereferenceability
at the MI level, so that they correspond to the equivalent concepts at
the IR level. (Currently an MI load is MI-invariant iff it's
IR-invariant and IR-dereferenceable.)
First step is renaming this function.
Reviewers: chandlerc
Subscribers: MatzeB, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D23370
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/lib/CodeGen/MachineCSE.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Sep 9 20:03:20 2016
@@ -1110,12 +1110,14 @@ public:
/// ordered or volatile memory references.
bool hasOrderedMemoryRef() const;
- /// Return true if this instruction is loading from a
- /// location whose value is invariant across the function. For example,
- /// loading a value from the constant pool or from the argument area of
- /// a function if it does not change. This should only return true of *all*
- /// loads the instruction does are invariant (if it does multiple loads).
- bool isInvariantLoad(AliasAnalysis *AA) const;
+ /// Return true if this load instruction never traps and points to a memory
+ /// location whose value doesn't change during the execution of this function.
+ ///
+ /// Examples include loading a value from the constant pool or from the
+ /// argument area of a function (if it does not change). If the instruction
+ /// does multiple loads, this returns true only if all of the loads are
+ /// dereferenceable and invariant.
+ bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
/// If the specified instruction is a PHI that always merges together the
/// same virtual register, return the register, otherwise return 0.
Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Fri Sep 9 20:03:20 2016
@@ -346,7 +346,7 @@ bool MachineCSE::isCSECandidate(MachineI
// Okay, this instruction does a load. As a refinement, we allow the target
// to decide whether the loaded value is actually a constant. If so, we can
// actually use it as a load.
- if (!MI->isInvariantLoad(AA))
+ if (!MI->isDereferenceableInvariantLoad(AA))
// FIXME: we should be able to hoist loads with no other side effects if
// there are no other instructions which can change memory in this loop.
// This is a trivial form of alias analysis.
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Sep 9 20:03:20 2016
@@ -1531,7 +1531,7 @@ bool MachineInstr::isSafeToMove(AliasAna
// destination. The check for isInvariantLoad gives the targe the chance to
// classify the load as always returning a constant, e.g. a constant pool
// load.
- if (mayLoad() && !isInvariantLoad(AA))
+ if (mayLoad() && !isDereferenceableInvariantLoad(AA))
// Otherwise, this is a real load. If there is a store between the load and
// end of block, we can't move it.
return !SawStore;
@@ -1562,12 +1562,10 @@ bool MachineInstr::hasOrderedMemoryRef()
});
}
-/// isInvariantLoad - Return true if this instruction is loading from a
-/// location whose value is invariant across the function. For example,
-/// loading a value from the constant pool or from the argument area
-/// of a function if it does not change. This should only return true of
-/// *all* loads the instruction does are invariant (if it does multiple loads).
-bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
+/// isDereferenceableInvariantLoad - Return true if this instruction will never
+/// trap and is loading from a location whose value is invariant across a run of
+/// this function.
+bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
// If the instruction doesn't load at all, it isn't an invariant load.
if (!mayLoad())
return false;
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Sep 9 20:03:20 2016
@@ -1138,7 +1138,8 @@ bool MachineLICM::IsProfitableToHoist(Ma
// High register pressure situation, only hoist if the instruction is going
// to be remat'ed.
- if (!TII->isTriviallyReMaterializable(MI, AA) && !MI.isInvariantLoad(AA)) {
+ if (!TII->isTriviallyReMaterializable(MI, AA) &&
+ !MI.isDereferenceableInvariantLoad(AA)) {
DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
return false;
}
@@ -1157,7 +1158,7 @@ MachineInstr *MachineLICM::ExtractHoista
// If not, we may be able to unfold a load and hoist that.
// First test whether the instruction is loading from an amenable
// memory location.
- if (!MI->isInvariantLoad(AA))
+ if (!MI->isDereferenceableInvariantLoad(AA))
return nullptr;
// Next determine the register class for a temporary register.
Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Fri Sep 9 20:03:20 2016
@@ -997,7 +997,7 @@ static bool isSuccOrder(SUnit *SUa, SUni
static bool isDependenceBarrier(MachineInstr &MI, AliasAnalysis *AA) {
return MI.isCall() || MI.hasUnmodeledSideEffects() ||
(MI.hasOrderedMemoryRef() &&
- (!MI.mayLoad() || !MI.isInvariantLoad(AA)));
+ (!MI.mayLoad() || !MI.isDereferenceableInvariantLoad(AA)));
}
/// Return the underlying objects for the memory references of an instruction.
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Fri Sep 9 20:03:20 2016
@@ -554,7 +554,7 @@ void ScheduleDAGInstrs::addVRegUseDeps(S
/// (like a call or something with unmodeled side effects).
static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
return MI->isCall() || MI->hasUnmodeledSideEffects() ||
- (MI->hasOrderedMemoryRef() && !MI->isInvariantLoad(AA));
+ (MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad(AA));
}
/// This returns true if the two MIs need a chain edge between them.
@@ -1023,7 +1023,8 @@ void ScheduleDAGInstrs::buildSchedGraph(
}
// If it's not a store or a variant load, we're done.
- if (!MI.mayStore() && !(MI.mayLoad() && !MI.isInvariantLoad(AA)))
+ if (!MI.mayStore() &&
+ !(MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA)))
continue;
// Always add dependecy edge to BarrierChain if present.
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp Fri Sep 9 20:03:20 2016
@@ -866,7 +866,7 @@ bool TargetInstrInfo::isReallyTriviallyR
return false;
// Avoid instructions which load from potentially varying memory.
- if (MI.mayLoad() && !MI.isInvariantLoad(AA))
+ if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
return false;
// If any of the registers accessed are non-constant, conservatively assume
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp Fri Sep 9 20:03:20 2016
@@ -130,7 +130,7 @@ static void Query(const MachineInstr &MI
return;
// Check for loads.
- if (MI.mayLoad() && !MI.isInvariantLoad(&AA))
+ if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(&AA))
Read = true;
// Check for stores.
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=281125&r1=281124&r2=281125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Sep 9 20:03:20 2016
@@ -2654,7 +2654,7 @@ bool X86InstrInfo::isReallyTriviallyReMa
MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
- MI.isInvariantLoad(AA)) {
+ MI.isDereferenceableInvariantLoad(AA)) {
unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
if (BaseReg == 0 || BaseReg == X86::RIP)
return true;
More information about the llvm-commits
mailing list