[llvm] r281037 - GlobalISel: remove G_TYPE and G_PHI
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 9 04:47:32 PDT 2016
Author: tnorthover
Date: Fri Sep 9 06:47:31 2016
New Revision: 281037
URL: http://llvm.org/viewvc/llvm-project?rev=281037&view=rev
Log:
GlobalISel: remove G_TYPE and G_PHI
These instructions were only necessary when type information was stored in the
MachineInstr (because only generic MachineInstrs possessed a type). Now that
it's in MachineRegisterInfo, COPY and PHI work fine.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/include/llvm/Target/GenericOpcodes.td
llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Sep 9 06:47:31 2016
@@ -779,10 +779,7 @@ public:
&& getOperand(1).isImm();
}
- bool isPHI() const {
- return getOpcode() == TargetOpcode::PHI ||
- getOpcode() == TargetOpcode::G_PHI;
- }
+ bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Fri Sep 9 06:47:31 2016
@@ -85,12 +85,6 @@ def G_FCONSTANT : Instruction {
let hasSideEffects = 0;
}
-def G_TYPE : Instruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins unknown:$imm);
- let hasSideEffects = 0;
-}
-
//------------------------------------------------------------------------------
// Binary ops.
//------------------------------------------------------------------------------
@@ -415,13 +409,6 @@ def G_INTRINSIC_W_SIDE_EFFECTS : Instruc
let mayStore = 1;
}
-// PHI node bearing an LLT.
-def G_PHI : Instruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins variable_ops);
- let hasSideEffects = 0;
-}
-
//------------------------------------------------------------------------------
// Branches.
//------------------------------------------------------------------------------
Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Fri Sep 9 06:47:31 2016
@@ -333,12 +333,6 @@ HANDLE_TARGET_OPCODE(G_SITOFP)
/// Generic unsigned-int to float conversion
HANDLE_TARGET_OPCODE(G_UITOFP)
-/// Generic type specifier for untyped registers.
-HANDLE_TARGET_OPCODE(G_TYPE)
-
-/// Generic PHI node (so that the type of the vreg can be set).
-HANDLE_TARGET_OPCODE(G_PHI)
-
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Fri Sep 9 06:47:31 2016
@@ -385,7 +385,7 @@ bool IRTranslator::translateStaticAlloca
bool IRTranslator::translatePHI(const User &U) {
const PHINode &PI = cast<PHINode>(U);
- auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI);
+ auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
MIB.addDef(getOrCreateVReg(PI));
PendingPHIs.emplace_back(&PI, MIB.getInstr());
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp Fri Sep 9 06:47:31 2016
@@ -33,11 +33,6 @@ MachineLegalizer::MachineLegalizer() : T
DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
DefaultActions[TargetOpcode::G_TRUNC] = Legal;
- // G_TYPE and G_PHI are essentially an annotated COPY/PHI instructions so
- // they're always legal.
- DefaultActions[TargetOpcode::G_TYPE] = Legal;
- DefaultActions[TargetOpcode::G_PHI] = Legal;
-
DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Fri Sep 9 06:47:31 2016
@@ -224,8 +224,7 @@ RegisterBankInfo::getInstrMappingImpl(co
bool CompleteMapping = true;
// For copies we want to walk over the operands and try to find one
// that has a register bank.
- bool isCopyLike =
- MI.isCopy() || MI.isPHI() || MI.getOpcode() == TargetOpcode::G_TYPE;
+ bool isCopyLike = MI.isCopy() || MI.isPHI();
// Remember the register bank for reuse for copy-like instructions.
const RegisterBank *RegBank = nullptr;
// Remember the size of the register for reuse for copy-like instructions.
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Fri Sep 9 06:47:31 2016
@@ -908,8 +908,7 @@ void MachineVerifier::visitMachineInstrB
}
// Generic opcodes must not have physical register operands.
- if (isPreISelGenericOpcode(MCID.getOpcode()) &&
- MCID.getOpcode() != TargetOpcode::G_TYPE) {
+ if (isPreISelGenericOpcode(MCID.getOpcode())) {
for (auto &Op : MI->operands()) {
if (Op.isReg() && TargetRegisterInfo::isPhysicalRegister(Op.getReg()))
report("Generic instruction cannot have physical register", MI);
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Fri Sep 9 06:47:31 2016
@@ -230,16 +230,6 @@ bool AArch64InstructionSelector::select(
return true;
}
- case TargetOpcode::G_TYPE: {
- I.setDesc(TII.get(TargetOpcode::COPY));
- return true;
- }
-
- case TargetOpcode::G_PHI: {
- I.setDesc(TII.get(TargetOpcode::PHI));
- return true;
- }
-
case TargetOpcode::G_FRAME_INDEX: {
// allocas and G_FRAME_INDEX are only supported in addrspace(0).
if (Ty != LLT::pointer(0)) {
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Fri Sep 9 06:47:31 2016
@@ -325,7 +325,7 @@ define void @intrinsics(i32 %cur, i32 %b
; CHECK: [[FALSE]]:
; CHECK: [[RES2:%[0-9]+]](s32) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s32) = G_PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
+; CHECK: [[RES:%[0-9]+]](s32) = PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
; CHECK: %w0 = COPY [[RES]]
define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
br i1 %tst, label %true, label %false
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir Fri Sep 9 06:47:31 2016
@@ -24,8 +24,8 @@ body: |
; CHECK-LABEL: name: test_scalar_and_small
; CHECK: %4(s8) = G_AND %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_AND %2, %3
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir Fri Sep 9 06:47:31 2016
@@ -34,7 +34,7 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- %0(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
; CHECK: %1(s1) = G_TRUNC %0
; CHECK: %2(s8) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir Fri Sep 9 06:47:31 2016
@@ -21,8 +21,8 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x0
%2(s32) = G_TRUNC %0
%3(s32) = G_TRUNC %1
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir Fri Sep 9 06:47:31 2016
@@ -15,10 +15,10 @@ body: |
bb.0:
liveins: %x0
; CHECK-LABEL: name: test_copy
- ; CHECK: %0(s64) = G_TYPE %x0
+ ; CHECK: %0(s64) = COPY %x0
; CHECK-NEXT: %x0 = COPY %0
- %0(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
%x0 = COPY %0
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir Fri Sep 9 06:47:31 2016
@@ -24,8 +24,8 @@ body: |
; CHECK-LABEL: name: test_scalar_mul_small
; CHECK: %4(s8) = G_MUL %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_MUL %2, %3
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir Fri Sep 9 06:47:31 2016
@@ -24,8 +24,8 @@ body: |
; CHECK-LABEL: name: test_scalar_or_small
; CHECK: %4(s8) = G_OR %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_OR %2, %3
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir Fri Sep 9 06:47:31 2016
@@ -24,8 +24,8 @@ body: |
; CHECK-LABEL: name: test_scalar_xor_small
; CHECK: %4(s8) = G_XOR %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_XOR %2, %3
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir Fri Sep 9 06:47:31 2016
@@ -9,7 +9,7 @@
...
---
# CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
-# CHECK: instruction: %vreg0<def>(s64) = G_TYPE
+# CHECK: instruction: %vreg0<def>(s64) = COPY
# CHECK: operand 0: %vreg0<def>
name: test
regBankSelected: true
@@ -18,5 +18,5 @@ registers:
body: |
bb.0:
liveins: %x0
- %0(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir?rev=281037&r1=281036&r2=281037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir Fri Sep 9 06:47:31 2016
@@ -19,7 +19,7 @@ registers:
body: |
bb.0:
liveins: %x0
- %0 = G_TYPE %x0
+ %0 = COPY %x0
; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
; CHECK: instruction: %vreg1<def> = G_ADD
More information about the llvm-commits
mailing list