[PATCH] D24130: [RegisterScavenger] Remove aliasing registers of operands from the candidate set

[Silviu Baranga via llvm-commits]

Hi Quentin,

I'm using the former. The problem can be reproduced by running on an existing test:

llc -mtriple=aarch64-unknown -run-pass prologepilog -run-before ../llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir -o -

It is entirely possible that I might be missing something obvious.

I'll file a PR.

Cheers,
Silviu

> -----Original Message-----
> From: qcolombet at apple.com [mailto:qcolombet at apple.com]
> Sent: 07 September 2016 18:53
> To: reviews+D24130+public+e18a1f842446f3da at reviews.llvm.org
> Cc: Silviu Baranga; matze at braunis.de; hfinkel at anl.gov; llvm-
> commits at lists.llvm.org
> Subject: Re: [PATCH] D24130: [RegisterScavenger] Remove aliasing registers
> of operands from the candidate set
>
> Hi Silviu,
>
> Thanks for given a try to the mir testing infrastructure.
>
> With Matthias we are working on productizing it and that would help if you
> could file a PR for the seg fault.
> Have you used -run-pass PEI, or run-before/after?
> The latter has some strange failure because of unmodeled dependencies
> between passes.
>
> Cheers,
> Q.
> > On Sep 7, 2016, at 9:00 AM, silviu.baranga at arm.com wrote:
> >
> > sbaranga added a comment.
> >
> > I've investigated using MIR for getting a test case. The problem that I
> currently have with this is that I'm unable to run the PEI pass (where the
> problem is happening). If I try to do this I get a segfault in the stack protector
> pass. The problem seems to be that the TargetMachine is null. I'm not sure if
> this is something specific to PEI - but there doesn't seem to be any other
> regression tests that tries to run just this pass.
> >
> > Here are the conditions that would trigger this bug:
> > We need to have a huge stack frame and a load or store to a stack location
> such that the location is far enough from the stack pointer and we need to
> scavenge a register to form the address. In order to avoid the heuristics from
> the register scavenger, all other registers except the one we want should be
> live. Our instruction should load or store a sub-register of the address
> register (for example str w0, [x0]).
> >
> >
> > https://reviews.llvm.org/D24130
> >
> >
> >

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