[llvm] r280813 - [X86][SSE] Added or combine tests for known bits of vectors

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Sep  7 09:49:50 2016
New Revision: 280813

URL: http://llvm.org/viewvc/llvm-project?rev=280813&view=rev
Log:
[X86][SSE] Added or combine tests for known bits of vectors

Part of the yak shaving for D24253

Modified:
    llvm/trunk/test/CodeGen/X86/combine-or.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-or.ll?rev=280813&r1=280812&r2=280813&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-or.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-or.ll Wed Sep  7 09:49:50 2016
@@ -415,3 +415,54 @@ define <4 x i32> @test2f(<4 x i32> %a, <
   %or = or <4 x i32> %shuf1, %shuf2
   ret <4 x i32> %or
 }
+
+; (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
+
+define <2 x i64> @or_and_v2i64(<2 x i64> %a0) {
+; CHECK-LABEL: or_and_v2i64:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = and <2 x i64> %a0, <i64 1, i64 1>
+  %2 = or <2 x i64> %1, <i64 3, i64 3>
+  ret <2 x i64> %2
+}
+
+define <4 x i32> @or_and_v4i32(<4 x i32> %a0) {
+; CHECK-LABEL: or_and_v4i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = and <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
+  %2 = or <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
+  ret <4 x i32> %2
+}
+
+; fold (or x, c) -> c iff (x & ~c) == 0
+
+define <2 x i64> @or_zext_v2i32(<2 x i32> %a0) {
+; CHECK-LABEL: or_zext_v2i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; CHECK-NEXT:    por {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = zext <2 x i32> %a0 to <2 x i64>
+  %2 = or <2 x i64> %1, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %2
+}
+
+define <4 x i32> @or_zext_v4i16(<4 x i16> %a0) {
+; CHECK-LABEL: or_zext_v4i16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; CHECK-NEXT:    por {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = zext <4 x i16> %a0 to <4 x i32>
+  %2 = or <4 x i32> %1, <i32 65536, i32 65536, i32 65536, i32 65536>
+  ret <4 x i32> %2
+}
+