[PATCH] D23402: AMDGPU/SI: Teach SIInstrInfo::FoldImmediate() to fold immediates into copies

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL280744: AMDGPU/SI: Teach SIInstrInfo::FoldImmediate() to fold immediates into copies (authored by tstellar).

Changed prior to commit:
  https://reviews.llvm.org/D23402?vs=70418&id=70461#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D23402

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td

Index: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
+++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
@@ -25,6 +25,7 @@
   let SALU = 1;
   let SOP1 = 1;
   let SchedRW = [WriteSALU];
+  let UseNamedOperandTable = 1;
 
   string Mnemonic = opName;
   string AsmOperands = asmOps;
@@ -1100,4 +1101,4 @@
 def S_SETREG_B32_vi        : SOPK_Real_vi <0x12, S_SETREG_B32>;
 //def S_GETREG_REGRD_B32_vi  : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
 def S_SETREG_IMM32_B32_vi  : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
-                             Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
\ No newline at end of file
+                             Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1184,14 +1184,39 @@
   MI.RemoveOperand(Src0ModIdx);
 }
 
-// TODO: Maybe this should be removed this and custom fold everything in
-// SIFoldOperands?
 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
                                 unsigned Reg, MachineRegisterInfo *MRI) const {
   if (!MRI->hasOneNonDBGUse(Reg))
     return false;
 
   unsigned Opc = UseMI.getOpcode();
+  if (Opc == AMDGPU::COPY) {
+    bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
+    switch (DefMI.getOpcode()) {
+    default:
+      return false;
+    case AMDGPU::S_MOV_B64:
+      // TODO: We could fold 64-bit immediates, but this get compilicated
+      // when there are sub-registers.
+      return false;
+
+    case AMDGPU::V_MOV_B32_e32:
+    case AMDGPU::S_MOV_B32:
+      break;
+    }
+    unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
+    const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
+    assert(ImmOp);
+    // FIXME: We could handle FrameIndex values here.
+    if (!ImmOp->isImm()) {
+      return false;
+    }
+    UseMI.setDesc(get(NewOpc));
+    UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
+    UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
+    return true;
+  }
+
   if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
     // Don't fold if we are using source modifiers. The new VOP2 instructions
     // don't have them.


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