[PATCH] D24221: AVX512F: FMA intrinsic + FNEG - sequence optimization

[Sanjay Patel via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM - see inline comments for some nits.


================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:30303
@@ +30302,3 @@
+///
+/// Fp-negation node may have different forms: FNEG(x) or FXOR (x, 0x80000000).
+/// AVX512F does not have FXOR, so FNEG is lowered as
----------------
Fp -> FP

================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:30307
@@ +30306,3 @@
+/// In this case we go though all bitcasts.
+SDValue isFNEG(SDNode *N) {
+  if (N->getOpcode() == ISD::FNEG)
----------------
static?

================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:30877
@@ -30866,4 +30876,3 @@
 
-  bool NegA = isFNEG(A.getNode());
-  bool NegB = isFNEG(B.getNode());
-  bool NegC = isFNEG(C.getNode());
+  auto invertIfNegative = [](SDValue& V) {
+    SDValue NegVal = isFNEG(V.getNode());
----------------
formatting: SDValue &V

================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:30878-30879
@@ +30877,4 @@
+  auto invertIfNegative = [](SDValue& V) {
+    SDValue NegVal = isFNEG(V.getNode());
+    if (NegVal) {
+      V = NegVal;
----------------
combine to one line? if (SDValue Negval = isFNEG...)


Repository:
  rL LLVM

https://reviews.llvm.org/D24221