[PATCH] D24260: AMDGPU: Sign extend constants when splitting them
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 6 09:29:55 PDT 2016
arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added subscribers: llvm-commits, AMDGPU.
Herald added subscribers: nhaehnle, wdng, arsenm.
This will confuse later passes which try to look at the immediate value and don't truncate first.
https://reviews.llvm.org/D24260
Files:
lib/Target/AMDGPU/SIInstrInfo.cpp
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1973,11 +1973,10 @@
unsigned SubIdx,
const TargetRegisterClass *SubRC) const {
if (Op.isImm()) {
- // XXX - Is there a better way to do this?
if (SubIdx == AMDGPU::sub0)
- return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
+ return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
if (SubIdx == AMDGPU::sub1)
- return MachineOperand::CreateImm(Op.getImm() >> 32);
+ return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm() >> 32));
llvm_unreachable("Unhandled register index for immediate");
}
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