[PATCH] D24259: [mips] Disable the TImode shift libcalls for 32-bit targets.

[Vasileios Kalintiris via llvm-commits]

vkalintiris created this revision.
vkalintiris added a reviewer: sdardis.
vkalintiris added a subscriber: llvm-commits.
Herald added a subscriber: sdardis.

The o32 ABI doesn't not support the TImode helpers. For the time being,
disable just the shift libcalls as they break recursive builds on MIPS.

https://reviews.llvm.org/D24259

Files:
  lib/Target/Mips/MipsISelLowering.cpp
  test/CodeGen/Mips/llvm-ir/ashr.ll
  test/CodeGen/Mips/llvm-ir/lshr.ll
  test/CodeGen/Mips/llvm-ir/shl.ll

Index: test/CodeGen/Mips/llvm-ir/shl.ll
===================================================================
--- test/CodeGen/Mips/llvm-ir/shl.ll
+++ test/CodeGen/Mips/llvm-ir/shl.ll
@@ -169,7 +169,9 @@
 entry:
 ; ALL-LABEL: shl_i128:
 
-  ; GP32:           lw        $25, %call16(__ashlti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__ashlti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__ashlti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsllv     $[[T1:[0-9]+]], $5, $7
@@ -216,8 +218,6 @@
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $3, $[[T9]], $[[T7]]
 
-  ; MM:             lw        $25, %call16(__ashlti3)($2)
-
   %r = shl i128 %a, %b
   ret i128 %r
 }
Index: test/CodeGen/Mips/llvm-ir/lshr.ll
===================================================================
--- test/CodeGen/Mips/llvm-ir/lshr.ll
+++ test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -153,7 +153,9 @@
 entry:
 ; ALL-LABEL: lshr_i128:
 
-  ; GP32:         lw      $25, %call16(__lshrti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__lshrti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__lshrti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
@@ -200,8 +202,6 @@
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $2, $[[T9]], $[[T7]]
 
-  ; MM:             lw        $25, %call16(__lshrti3)($2)
-
   %r = lshr i128 %a, %b
   ret i128 %r
 }
Index: test/CodeGen/Mips/llvm-ir/ashr.ll
===================================================================
--- test/CodeGen/Mips/llvm-ir/ashr.ll
+++ test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -162,7 +162,9 @@
 entry:
 ; ALL-LABEL: ashr_i128:
 
-  ; GP32:           lw        $25, %call16(__ashrti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__ashrti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__ashrti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrav     $[[T1:[0-9]+]], $4, $7
@@ -213,8 +215,6 @@
   ; 64R6:           jr        $ra
   ; 64R6:           or        $3, $[[T13]], $[[T12]]
 
-  ; MM:             lw        $25, %call16(__ashrti3)($2)
-
   %r = ashr i128 %a, %b
   ret i128 %r
 }
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -426,6 +426,13 @@
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::AssertZext);
 
+  if (ABI.IsO32()) {
+    // These libcalls are not available in 32-bit.
+    setLibcallName(RTLIB::SHL_I128, nullptr);
+    setLibcallName(RTLIB::SRL_I128, nullptr);
+    setLibcallName(RTLIB::SRA_I128, nullptr);
+  }
+
   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
 
   // The arguments on the stack are defined in terms of 4-byte slots on O32


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