[PATCH] D24253: [SelectionDAG] Add basic vector support to computeKnownBits and SimplifyDemandedBits

[Nirav Dave via llvm-commits]

niravd added a comment.

Is there a reason why you aren't keeping the known bits of a BUILD_VECTOR precise, i.e. concatenating each elements known bits?


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2035
@@ +2034,3 @@
+      // TODO: support per-element known bits.
+      if (i == 0) {
+        KnownOne = KnownOne2;
----------------
It would be clearer if you initialized KnownOne and KnownZero to all ones at the start of the loop and replace the conditional with the else case. 

================
Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:494
@@ +493,3 @@
+      // TODO: support per-element known bits.
+      if (i == 0) {
+        KnownOne = KnownOne2;
----------------
Same as above


Repository:
  rL LLVM

https://reviews.llvm.org/D24253