[PATCH] D24221: AVX512F: FMA intrinsic + FNEG - sequence optimization

[Elena Demikhovsky via llvm-commits]

delena added inline comments.

================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:30359-30361
@@ +30358,5 @@
+  SDValue Arg;
+  bool IsFNEGNode = isFNEG(N, &Arg);
+  if (!IsFNEGNode)
+    llvm_unreachable("Expected FNEG node");
+ 
----------------
spatel wrote:
> Can this be an assert?
> assert(IsFNEGNode && "Expected FNEG node"); 
It will fail on compilation in release mode:
bool IsFNEGNode = isFNEG(N, &Arg); - Unused variable IsFNEGNode
assert(IsFNEGNode && "Expected FNEG node");

================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:30307
@@ +30306,3 @@
+/// In this case we go though all bitcasts.
+bool isFNEG(SDNode *N, SDValue* Op0 = nullptr) {
+  if (N->getOpcode() == ISD::FNEG) {
----------------
spatel wrote:
> This interface feels awkward. The normal pattern is:
> static SDValue getFNeg(SDNode *N)
> 
> Ie, if there's no negated value, it will return the empty SDValue(), and the caller can use that as a bool value if it wants to.
Thanks! I was looking for a proper interface. You suggestion is better than all APIs that I tried till now.
I'll update the patch.

I still think that my first solution with late FNEG lowering was simpler.  We handle too many different patterns for XOR/FXOR.


Repository:
  rL LLVM

https://reviews.llvm.org/D24221