[PATCH] D24239: [RegScavenger] Check for sub- and super-registers of ones used by instructions

[Oliver Stannard via llvm-commits]

olista01 created this revision.
olista01 added reviewers: MatzeB, kparzysz, hfinkel.
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Previously, the register scavenger did not check sub- and
super-registers of those used by the current instruction, so we could
emit code which clobbered a live value when we scavenged a register to
materialise a stack slot address.

I've tried to create a smaller reproducer for this with no success.
Because this requires both large stack frames and high register
pressure, the test case that uncovered it is massive, and will not be a
good regression test as any change in register or stack slot allocation
would cause it to pass on a broken compiler. Does anyone know of a
better way to reproduce this? If not, would it be better to commit this
without a test than with a large, fragile test?

Repository:
  rL LLVM

https://reviews.llvm.org/D24239

Files:
  lib/CodeGen/RegisterScavenging.cpp
  test/CodeGen/AArch64/scavenge-sub-registers.ll

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