[llvm] r280647 - [Target] Remove the AvailableRegClasses vector from TargetLoweringBase. It was a private member with no code reading from it.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Mon Sep  5 01:43:00 2016
New Revision: 280647

URL: http://llvm.org/viewvc/llvm-project?rev=280647&view=rev
Log:
[Target] Remove the AvailableRegClasses vector from TargetLoweringBase. It was a private member with no code reading from it.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=280647&r1=280646&r2=280647&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Sep  5 01:43:00 2016
@@ -1409,15 +1409,12 @@ protected:
   /// that class natively.
   void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
     assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
-    AvailableRegClasses.push_back(std::make_pair(VT, RC));
     RegClassForVT[VT.SimpleTy] = RC;
   }
 
   /// Remove all register classes.
   void clearRegisterClasses() {
     std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
-
-    AvailableRegClasses.clear();
   }
 
   /// \brief Remove all operation actions.
@@ -2064,7 +2061,6 @@ private:
   LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
 
 private:
-  std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
 
   /// Targets can specify ISD nodes that they would like PerformDAGCombine
   /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this