[PATCH] D23155: Power9 - Part-word VSX integer scalar loads/stores and sign extend instructions

[Chuang-Yu Cheng via llvm-commits]

cycheng added inline comments.

================
Comment at: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp:450
@@ +449,3 @@
+    // names are "v0-v31", so we need to map "v0-v31" to "vs32-vs63"
+    // (Please synchronize with PPCAsmPrinter::printOperand)
+    if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg)) {
----------------
kbarton wrote:
> What does this comment mean?
> Does this need to be done? If not, can it be removed?
Because ISA3.0 add new VSX instruction formats, so couple of new VSX instructions (xsabsqp, xsnabsqp, ...) uses V registers.

When we want to print operand for VSX instructions, we have to know which register class it is.


```
    if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg)) {
```

if PPCII::UseVSXReg is true, then it means the VSX instruction use VSX registers (without any V registers.), so the following code will treat these register as VSX register.


```
      if (isVRRegister(Reg))
        Reg = PPC::VSX32 + (Reg - PPC::V0);
```
But because we use v0-v31 to represent vs32-vs63, so you will see the Reg is PPC::V0 - PPC::V31, so we get the offset value, and add that offset back to base PPC::VSX32.

The purpose here is, we want to translate v0-v31 back to vs32-vs63.

================
Comment at: lib/Target/PowerPC/PPCAsmPrinter.cpp:185
@@ +184,3 @@
+    // names are "v0-v31", so we need to map "v0-v31" to "vs32-vs63"
+    // (Please synchronize with PPCInstPrinter::printOperand)
+    if (MI->getDesc().TSFlags & PPCII::UseVSXReg) {
----------------
kbarton wrote:
> Extraneous comment?
Same logic as PPCInstPrinter::printOperand, maybe we can replace this comment with short one.



Repository:
  rL LLVM

https://reviews.llvm.org/D23155