[llvm] r280457 - [PowerPC] hasAndNotCompare should return true

[Hal Finkel via llvm-commits]

Author: hfinkel
Date: Thu Sep  1 21:58:25 2016
New Revision: 280457

URL: http://llvm.org/viewvc/llvm-project?rev=280457&view=rev
Log:
[PowerPC] hasAndNotCompare should return true

As Sanjay suggested when he added the hook, PPC should return true from
hasAndNotCompare. We have an efficient negated 'and' on PPC (which can feed a
compare).

Fixes PR27203.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/test/CodeGen/PowerPC/andc.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=280457&r1=280456&r2=280457&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Sep  1 21:58:25 2016
@@ -496,6 +496,10 @@ namespace llvm {
       return true;
     }
 
+    bool hasAndNotCompare(SDValue) const override {
+      return true;
+    }
+
     bool supportSplitCSR(MachineFunction *MF) const override {
       return
         MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&

Modified: llvm/trunk/test/CodeGen/PowerPC/andc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/andc.ll?rev=280457&r1=280456&r2=280457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/andc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/andc.ll Thu Sep  1 21:58:25 2016
@@ -1,18 +1,12 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin | FileCheck %s
 
-; TODO: These could use 'andc'.
-
 define i1 @and_cmp1(i32 %x, i32 %y) {
 ; CHECK-LABEL: and_cmp1:
-; CHECK:       ; BB#0:
-; CHECK-NEXT:    and r2, r3, r4
-; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    cmpw cr0, r2, r4
-; CHECK-NEXT:    bclr 12, 2, 0
-; CHECK-NEXT:  ; BB#1:
-; CHECK-NEXT:    li r3, 0
-; CHECK-NEXT:    blr
-;
+; CHECK: andc [[REG1:r[0-9]+]], r4, r3
+; CHECK: cntlzw   [[REG2:r[0-9]+]], [[REG1]]
+; CHECK: rlwinm r3, [[REG2]], 27, 31, 31
+; CHECK: blr
+
   %and = and i32 %x, %y
   %cmp = icmp eq i32 %and, %y
   ret i1 %cmp
@@ -20,17 +14,28 @@ define i1 @and_cmp1(i32 %x, i32 %y) {
 
 define i1 @and_cmp_const(i32 %x) {
 ; CHECK-LABEL: and_cmp_const:
-; CHECK:       ; BB#0:
-; CHECK-NEXT:    andi. r2, r3, 43
-; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    cmpwi r2, 43
-; CHECK-NEXT:    bclr 12, 2, 0
-; CHECK-NEXT:  ; BB#1:
-; CHECK-NEXT:    li r3, 0
-; CHECK-NEXT:    blr
-;
+; CHECK: li [[REG1:r[0-9]+]], 43
+; CHECK: andc [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK: cntlzw   [[REG3:r[0-9]+]], [[REG2]]
+; CHECK: rlwinm r3, [[REG3]], 27, 31, 31
+; CHECK: blr
+
   %and = and i32 %x, 43
   %cmp = icmp eq i32 %and, 43
   ret i1 %cmp
 }
 
+define i1 @foo(i32 %i) {
+; CHECK-LABEL: foo:
+; CHECK: lis [[REG1:r[0-9]+]], 4660
+; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 22136
+; CHECK: andc [[REG3:r[0-9]+]], [[REG2]], r3
+; CHECK: cntlzw  [[REG4:r[0-9]+]], [[REG3]]
+; CHECK: rlwinm r3, [[REG4]], 27, 31, 31
+; CHECK: blr
+
+  %and = and i32 %i, 305419896
+  %cmp = icmp eq i32 %and, 305419896
+  ret i1 %cmp
+}
+