[llvm] r280454 - [PowerPC] Add a pattern for a runtime bit check

[Hal Finkel via llvm-commits]

Author: hfinkel
Date: Thu Sep  1 21:34:44 2016
New Revision: 280454

URL: http://llvm.org/viewvc/llvm-project?rev=280454&view=rev
Log:
[PowerPC] Add a pattern for a runtime bit check

Following a suggestion by Sanjay, we should lower:

  %shl = shl i32 1, %y
  %and = and i32 %x, %shl
  %cmp = icmp eq i32 %and, %shl
  ret i1 %cmp

into:

  subfic r4, r4, 32
  rlwnm r3, r3, r4, 31, 31

Add this pattern and some associated patterns for the 64-bit case and the
not-equal case. Fixes PR27356.

Added:
    llvm/trunk/test/CodeGen/PowerPC/shift-cmp.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=280454&r1=280453&r2=280454&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Sep  1 21:34:44 2016
@@ -3185,6 +3185,46 @@ defm : ExtSetCCPat<SETLE,
                    OutPatFrag<(ops node:$in),
                               (RLDICL $in, 1, 63)> >;
 
+// An extended SETCC with shift amount.
+multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
+                            OutPatFrag rfrag, OutPatFrag rfrag8> {
+  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
+            (rfrag $s1, $sa)>;
+  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
+            (rfrag8 $s1, $sa)>;
+  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
+            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
+  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
+            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
+
+  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
+            (rfrag $s1, $sa)>;
+  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
+            (rfrag8 $s1, $sa)>;
+  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
+            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
+  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
+            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
+}
+
+defm : ExtSetCCShiftPat<SETNE,
+                        PatFrag<(ops node:$in, node:$sa, node:$cc),
+                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
+                        OutPatFrag<(ops node:$in, node:$sa),
+                                   (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,
+                        OutPatFrag<(ops node:$in, node:$sa),
+                                   (RLDCL $in, (SUBFIC $sa, 64), 63)> >;
+
+defm : ExtSetCCShiftPat<SETEQ,
+                        PatFrag<(ops node:$in, node:$sa, node:$cc),
+                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
+                        OutPatFrag<(ops node:$in, node:$sa),
+                                   (RLWNM (i32not $in),
+                                          (SUBFIC $sa, 32), 31, 31)>,
+                        OutPatFrag<(ops node:$in, node:$sa),
+                                   (RLDCL (i64not $in),
+                                          (SUBFIC $sa, 64), 63)> >;
+
 // SETCC for i32.
 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
           (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;

Added: llvm/trunk/test/CodeGen/PowerPC/shift-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/shift-cmp.ll?rev=280454&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/shift-cmp.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/shift-cmp.ll Thu Sep  1 21:34:44 2016
@@ -0,0 +1,54 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+define i1 @and_cmp_variable_power_of_two(i32 %x, i32 %y) {
+  %shl = shl i32 1, %y
+  %and = and i32 %x, %shl
+  %cmp = icmp eq i32 %and, %shl
+  ret i1 %cmp
+
+; CHECK-LABEL: @and_cmp_variable_power_of_two
+; CHECK: subfic 4, 4, 32
+; CHECK: rlwnm 3, 3, 4, 31, 31
+; CHECK: blr
+}
+
+define i1 @and_cmp_variable_power_of_two_64(i64 %x, i64 %y) {
+  %shl = shl i64 1, %y
+  %and = and i64 %x, %shl
+  %cmp = icmp eq i64 %and, %shl
+  ret i1 %cmp
+
+; CHECK-LABEL: @and_cmp_variable_power_of_two_64
+; CHECK: subfic 4, 4, 64
+; CHECK: rldcl 3, 3, 4, 63
+; CHECK: blr
+}
+
+define i1 @and_ncmp_variable_power_of_two(i32 %x, i32 %y) {
+  %shl = shl i32 1, %y
+  %and = and i32 %x, %shl
+  %cmp = icmp ne i32 %and, %shl
+  ret i1 %cmp
+
+; CHECK-LABEL: @and_ncmp_variable_power_of_two
+; CHECK-DAG: subfic 4, 4, 32
+; CHECK-DAG: nor [[REG:[0-9]+]], 3, 3
+; CHECK: rlwnm 3, [[REG]], 4, 31, 31
+; CHECK: blr
+}
+
+define i1 @and_ncmp_variable_power_of_two_64(i64 %x, i64 %y) {
+  %shl = shl i64 1, %y
+  %and = and i64 %x, %shl
+  %cmp = icmp ne i64 %and, %shl
+  ret i1 %cmp
+
+; CHECK-LABEL: @and_ncmp_variable_power_of_two_64
+; CHECK-DAG: subfic 4, 4, 64
+; CHECK-DAG: not [[REG:[0-9]+]], 3
+; CHECK: rldcl 3, [[REG]], 4, 63
+; CHECK: blr
+}
+