[llvm] r280412 - GlobalISel: add a G_PHI instruction to give phis a type.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 1 13:45:41 PDT 2016
Author: tnorthover
Date: Thu Sep 1 15:45:41 2016
New Revision: 280412
URL: http://llvm.org/viewvc/llvm-project?rev=280412&view=rev
Log:
GlobalISel: add a G_PHI instruction to give phis a type.
They're another source of generic vregs, which are going to need a type on the
definition when we remove the register width from MachineRegisterInfo.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/include/llvm/Target/GenericOpcodes.td
llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=280412&r1=280411&r2=280412&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Sep 1 15:45:41 2016
@@ -793,7 +793,10 @@ public:
&& getOperand(1).isImm();
}
- bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
+ bool isPHI() const {
+ return getOpcode() == TargetOpcode::PHI ||
+ getOpcode() == TargetOpcode::G_PHI;
+ }
bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=280412&r1=280411&r2=280412&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Thu Sep 1 15:45:41 2016
@@ -415,6 +415,13 @@ def G_INTRINSIC_W_SIDE_EFFECTS : Instruc
let mayStore = 1;
}
+// PHI node bearing an LLT.
+def G_PHI : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins variable_ops);
+ let hasSideEffects = 0;
+}
+
//------------------------------------------------------------------------------
// Branches.
//------------------------------------------------------------------------------
Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=280412&r1=280411&r2=280412&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Thu Sep 1 15:45:41 2016
@@ -336,6 +336,9 @@ HANDLE_TARGET_OPCODE(G_UITOFP)
/// Generic type specifier for untyped registers.
HANDLE_TARGET_OPCODE(G_TYPE)
+/// Generic PHI node (so that the type of the vreg can be set).
+HANDLE_TARGET_OPCODE(G_PHI)
+
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=280412&r1=280411&r2=280412&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Sep 1 15:45:41 2016
@@ -405,7 +405,7 @@ bool IRTranslator::translateStaticAlloca
bool IRTranslator::translatePHI(const User &U) {
const PHINode &PI = cast<PHINode>(U);
- MachineInstrBuilder MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
+ auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, LLT{*U.getType()});
MIB.addDef(getOrCreateVReg(PI));
PendingPHIs.emplace_back(&PI, MIB.getInstr());
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp?rev=280412&r1=280411&r2=280412&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp Thu Sep 1 15:45:41 2016
@@ -30,8 +30,10 @@ MachineLegalizer::MachineLegalizer() : T
DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
DefaultActions[TargetOpcode::G_TRUNC] = Legal;
- // G_TYPE is essentially an annotated COPY so it's always legal.
+ // G_TYPE and G_PHI are essentially an annotated COPY/PHI instructions so
+ // they're always legal.
DefaultActions[TargetOpcode::G_TYPE] = Legal;
+ DefaultActions[TargetOpcode::G_PHI] = Legal;
DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=280412&r1=280411&r2=280412&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Sep 1 15:45:41 2016
@@ -235,6 +235,12 @@ bool AArch64InstructionSelector::select(
return true;
}
+ case TargetOpcode::G_PHI: {
+ I.setDesc(TII.get(TargetOpcode::PHI));
+ I.removeTypes();
+ return true;
+ }
+
case TargetOpcode::G_FRAME_INDEX: {
// allocas and G_FRAME_INDEX are only supported in addrspace(0).
if (I.getType() != LLT::pointer(0)) {
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=280412&r1=280411&r2=280412&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Thu Sep 1 15:45:41 2016
@@ -325,7 +325,7 @@ define void @intrinsics(i32 %cur, i32 %b
; CHECK: [[FALSE]]:
; CHECK: [[RES2:%[0-9]+]](32) = G_LOAD { s32, p0 }
-; CHECK: [[RES:%[0-9]+]](32) = PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
+; CHECK: [[RES:%[0-9]+]](32) = G_PHI s32 [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
; CHECK: %w0 = COPY [[RES]]
define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
br i1 %tst, label %true, label %false
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