[llvm] r279956 - [AVX-512] Add 512-bit fabs tests with and without AVX512DQ.
Reid Kleckner via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 29 09:26:21 PDT 2016
This test fails on Windows:
http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/9916/steps/ninja%20check%202/logs/FAIL%3A%20LLVM%3A%3Avec_fabs.ll
C:\buildbot\slave-config\clang-x86-win2008-selfhost\llvm\test\CodeGen\X86\vec_fabs.ll:138:17:
error: expected string not found in input
; X32_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [nan,nan,nan,nan]
^
<stdin>:99:2: note: scanning from here
vmovaps .LCPI4_0, %ymm2 # ymm2 =
[1.#QNAN0e+00,1.#QNAN0e+00,1.#QNAN0e+00,1.#QNAN0e+00]
So apparently the MSVC CRT prints NaNs in a unique way.
On Sun, Aug 28, 2016 at 9:49 PM, Craig Topper via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Sun Aug 28 23:49:24 2016
> New Revision: 279956
>
> URL: http://llvm.org/viewvc/llvm-project?rev=279956&view=rev
> Log:
> [AVX-512] Add 512-bit fabs tests with and without AVX512DQ.
>
> Modified:
> llvm/trunk/test/CodeGen/X86/vec_fabs.ll
>
> Modified: llvm/trunk/test/CodeGen/X86/vec_fabs.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/X86/vec_fabs.ll?rev=279956&r1=279955&r2=279956&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/X86/vec_fabs.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vec_fabs.ll Sun Aug 28 23:49:24 2016
> @@ -1,8 +1,10 @@
> ; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s
> --check-prefix=X32
> -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck
> %s --check-prefix=X32
> -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck
> %s --check-prefix=X64
> -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f |
> FileCheck %s --check-prefix=X64
> +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s
> --check-prefix=X32 --check-prefix=X32_AVX
> +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl |
> FileCheck %s --check-prefix=X32 --check-prefix=X32_AVX512VL
> +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512dq,+avx512vl
> | FileCheck %s --check-prefix=X32 --check-prefix=X32_AVX512VLDQ
> +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck
> %s --check-prefix=X64 --check-prefix=X64_AVX
> +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl |
> FileCheck %s --check-prefix=X64 --check-prefix=X64_AVX512VL
> +; RUN: llc < %s -mtriple=x86_64-unknown-unknown
> -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64
> --check-prefix=X64_AVX512VLDQ
>
> define <2 x double> @fabs_v2f64(<2 x double> %p) {
> ; X32-LABEL: fabs_v2f64:
> @@ -64,6 +66,84 @@ define <8 x float> @fabs_v8f32(<8 x floa
> }
> declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
>
> +define <8 x double> @fabs_v8f64(<8 x double> %p) {
> +; X32_AVX-LABEL: fabs_v8f64:
> +; X32_AVX: # BB#0:
> +; X32_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [9223372036854775807,
> 9223372036854775807,9223372036854775807,9223372036854775807]
> +; X32_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
> +; X32_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
> +; X32_AVX-NEXT: retl
> +;
> +; X32_AVX512VL-LABEL: fabs_v8f64:
> +; X32_AVX512VL: # BB#0:
> +; X32_AVX512VL-NEXT: vpandq {{\.LCPI.*}}, %zmm0, %zmm0
> +; X32_AVX512VL-NEXT: retl
> +;
> +; X32_AVX512VLDQ-LABEL: fabs_v8f64:
> +; X32_AVX512VLDQ: # BB#0:
> +; X32_AVX512VLDQ-NEXT: vandps {{\.LCPI.*}}, %zmm0, %zmm0
> +; X32_AVX512VLDQ-NEXT: retl
> +;
> +; X64_AVX-LABEL: fabs_v8f64:
> +; X64_AVX: # BB#0:
> +; X64_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [9223372036854775807,
> 9223372036854775807,9223372036854775807,9223372036854775807]
> +; X64_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
> +; X64_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
> +; X64_AVX-NEXT: retq
> +;
> +; X64_AVX512VL-LABEL: fabs_v8f64:
> +; X64_AVX512VL: # BB#0:
> +; X64_AVX512VL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
> +; X64_AVX512VL-NEXT: retq
> +;
> +; X64_AVX512VLDQ-LABEL: fabs_v8f64:
> +; X64_AVX512VLDQ: # BB#0:
> +; X64_AVX512VLDQ-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
> +; X64_AVX512VLDQ-NEXT: retq
> + %t = call <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
> + ret <8 x double> %t
> +}
> +declare <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
> +
> +define <16 x float> @fabs_v16f32(<16 x float> %p) {
> +; X32_AVX-LABEL: fabs_v16f32:
> +; X32_AVX: # BB#0:
> +; X32_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [2147483647,2147483647,
> 2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
> +; X32_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
> +; X32_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
> +; X32_AVX-NEXT: retl
> +;
> +; X32_AVX512VL-LABEL: fabs_v16f32:
> +; X32_AVX512VL: # BB#0:
> +; X32_AVX512VL-NEXT: vpandq {{\.LCPI.*}}, %zmm0, %zmm0
> +; X32_AVX512VL-NEXT: retl
> +;
> +; X32_AVX512VLDQ-LABEL: fabs_v16f32:
> +; X32_AVX512VLDQ: # BB#0:
> +; X32_AVX512VLDQ-NEXT: vandps {{\.LCPI.*}}, %zmm0, %zmm0
> +; X32_AVX512VLDQ-NEXT: retl
> +;
> +; X64_AVX-LABEL: fabs_v16f32:
> +; X64_AVX: # BB#0:
> +; X64_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [2147483647,2147483647,
> 2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
> +; X64_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
> +; X64_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
> +; X64_AVX-NEXT: retq
> +;
> +; X64_AVX512VL-LABEL: fabs_v16f32:
> +; X64_AVX512VL: # BB#0:
> +; X64_AVX512VL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
> +; X64_AVX512VL-NEXT: retq
> +;
> +; X64_AVX512VLDQ-LABEL: fabs_v16f32:
> +; X64_AVX512VLDQ: # BB#0:
> +; X64_AVX512VLDQ-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0
> +; X64_AVX512VLDQ-NEXT: retq
> + %t = call <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
> + ret <16 x float> %t
> +}
> +declare <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
> +
> ; PR20354: when generating code for a vector fabs op,
> ; make sure that we're only turning off the sign bit of each float value.
> ; No constant pool loads or vector ops are needed for the fabs of a
>
>
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