[PATCH] D23862: AMDGPU/SI: Improve register allocation hints for sopk instructions

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL279968: AMDGPU/SI: Improve register allocation hints for sopk instructions (authored by tstellar).

Changed prior to commit:
  https://reviews.llvm.org/D23862?vs=69193&id=69563#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D23862

Files:
  llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/trunk/test/CodeGen/AMDGPU/shl_add_constant.ll

Index: llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -282,6 +282,7 @@
         if (TargetRegisterInfo::isVirtualRegister(Dest.getReg()) &&
             Src0.isReg()) {
           MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg());
+          MRI.setRegAllocationHint(Src0.getReg(), 0, Dest.getReg());
           continue;
         }
 
Index: llvm/trunk/test/CodeGen/AMDGPU/shl_add_constant.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/shl_add_constant.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/shl_add_constant.ll
@@ -74,8 +74,8 @@
 ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
 ; SI: s_add_i32 [[TMP:s[0-9]+]], [[Y]], [[SHL3]]
-; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
+; SI: s_addk_i32 [[TMP]], 0x3d8
+; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]]
 ; SI: buffer_store_dword [[VRESULT]]
 
 define void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {


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