[llvm] r279899 - AMDGPU: Remove register operand from si_mask_branch

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Fri Aug 26 19:42:21 2016
New Revision: 279899

URL: http://llvm.org/viewvc/llvm-project?rev=279899&view=rev
Log:
AMDGPU: Remove register operand from si_mask_branch

It isn't used for anything, and is also misleading since
it could be spilled at the end of the block, so it can't be relied
on. There ends up being a verifier error about using an undefined
register since the spill kills the register.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
    llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=279899&r1=279898&r2=279899&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Fri Aug 26 19:42:21 2016
@@ -1803,7 +1803,7 @@ let hasSideEffects = 1 in {
 // Dummy terminator instruction to use after control flow instructions
 // replaced with exec mask operations.
 def SI_MASK_BRANCH : PseudoInstSI <
-  (outs), (ins brtarget:$target, SReg_64:$dst)> {
+  (outs), (ins brtarget:$target)> {
   let isBranch = 0;
   let isTerminator = 1;
   let isBarrier = 0;

Modified: llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp?rev=279899&r1=279898&r2=279899&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp Fri Aug 26 19:42:21 2016
@@ -136,8 +136,7 @@ void SILowerControlFlow::emitIf(MachineI
   // be used later when inserting skips.
   MachineInstr *NewBr =
     BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
-    .addOperand(MI.getOperand(2))
-    .addReg(SaveExecReg, getKillRegState(SaveExec.isKill()));
+    .addOperand(MI.getOperand(2));
 
   if (!LIS) {
     MI.eraseFromParent();
@@ -196,8 +195,7 @@ void SILowerControlFlow::emitElse(Machin
   // Insert a pseudo terminator to help keep the verifier happy.
   MachineInstr *Branch =
     BuildMI(MBB, Term, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
-    .addMBB(DestBB)
-    .addReg(DstReg);
+    .addMBB(DestBB);
 
   if (!LIS) {
     MI.eraseFromParent();