[llvm] r279843 - GlobalISel: simplify G_ICMP legalization regime.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 26 10:46:17 PDT 2016
Author: tnorthover
Date: Fri Aug 26 12:46:17 2016
New Revision: 279843
URL: http://llvm.org/viewvc/llvm-project?rev=279843&view=rev
Log:
GlobalISel: simplify G_ICMP legalization regime.
It's unclear how the old
%res(32) = G_ICMP { s32, s32 } intpred(eq), %0, %1
is actually different from an s1 verison
%res(1) = G_ICMP { s1, s32 } intpred(eq), %0, %1
so we'll remove it for now.
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp?rev=279843&r1=279842&r2=279843&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp Fri Aug 26 12:46:17 2016
@@ -234,38 +234,28 @@ MachineLegalizeHelper::widenScalar(Machi
return Legalized;
}
case TargetOpcode::G_ICMP: {
- if (TypeIdx == 0) {
- unsigned TstExt = MRI.createGenericVirtualRegister(WideSize);
- MIRBuilder.buildICmp(
- {WideTy, MI.getType(1)},
- static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
- TstExt, MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
- MIRBuilder.buildTrunc({Ty, WideTy}, MI.getOperand(0).getReg(), TstExt);
- MI.eraseFromParent();
- return Legalized;
+ assert(TypeIdx == 1 && "unable to legalize predicate");
+ bool IsSigned = CmpInst::isSigned(
+ static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
+ unsigned Op0Ext = MRI.createGenericVirtualRegister(WideSize);
+ unsigned Op1Ext = MRI.createGenericVirtualRegister(WideSize);
+ if (IsSigned) {
+ MIRBuilder.buildSExt({WideTy, MI.getType(1)}, Op0Ext,
+ MI.getOperand(2).getReg());
+ MIRBuilder.buildSExt({WideTy, MI.getType(1)}, Op1Ext,
+ MI.getOperand(3).getReg());
} else {
- bool IsSigned = CmpInst::isSigned(
- static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
- unsigned Op0Ext = MRI.createGenericVirtualRegister(WideSize);
- unsigned Op1Ext = MRI.createGenericVirtualRegister(WideSize);
- if (IsSigned) {
- MIRBuilder.buildSExt({WideTy, MI.getType(1)}, Op0Ext,
- MI.getOperand(2).getReg());
- MIRBuilder.buildSExt({WideTy, MI.getType(1)}, Op1Ext,
- MI.getOperand(3).getReg());
- } else {
- MIRBuilder.buildZExt({WideTy, MI.getType(1)}, Op0Ext,
- MI.getOperand(2).getReg());
- MIRBuilder.buildZExt({WideTy, MI.getType(1)}, Op1Ext,
- MI.getOperand(3).getReg());
- }
- MIRBuilder.buildICmp(
- {MI.getType(0), WideTy},
- static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
- MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
- MI.eraseFromParent();
- return Legalized;
+ MIRBuilder.buildZExt({WideTy, MI.getType(1)}, Op0Ext,
+ MI.getOperand(2).getReg());
+ MIRBuilder.buildZExt({WideTy, MI.getType(1)}, Op1Ext,
+ MI.getOperand(3).getReg());
}
+ MIRBuilder.buildICmp(
+ {MI.getType(0), WideTy},
+ static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
+ MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
+ MI.eraseFromParent();
+ return Legalized;
}
}
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp?rev=279843&r1=279842&r2=279843&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp Fri Aug 26 12:46:17 2016
@@ -89,17 +89,12 @@ AArch64MachineLegalizer::AArch64MachineL
setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar);
- // Comparisons: we produce a result in s32 with undefined high-bits for
- // now. Values being compared can be 32 or 64-bits.
- for (auto CmpOp : { G_ICMP }) {
- setAction({CmpOp, 0, s32}, Legal);
- setAction({CmpOp, 1, s32}, Legal);
- setAction({CmpOp, 1, s64}, Legal);
+ setAction({G_ICMP, s1}, Legal);
+ setAction({G_ICMP, 1, s32}, Legal);
+ setAction({G_ICMP, 1, s64}, Legal);
- for (auto Ty : {s1, s8, s16}) {
- setAction({CmpOp, 0, Ty}, WidenScalar);
- setAction({CmpOp, 1, Ty}, WidenScalar);
- }
+ for (auto Ty : {s1, s8, s16}) {
+ setAction({G_ICMP, 1, Ty}, WidenScalar);
}
// Extensions
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir?rev=279843&r1=279842&r2=279843&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir Fri Aug 26 12:46:17 2016
@@ -30,28 +30,11 @@ body: |
%2(8) = G_TRUNC { s8, s64 } %0
%3(8) = G_TRUNC { s8, s64 } %1
- ; CHECK: [[TST32:%[0-9]+]](32) = G_ICMP { s32, s64 } intpred(sge), %0, %1
- ; CHECK: %4(1) = G_TRUNC { s1, s32 } [[TST32]]
+ ; CHECK: %4(1) = G_ICMP { s1, s64 } intpred(sge), %0, %1
%4(1) = G_ICMP { s1, s64 } intpred(sge), %0, %1
; CHECK: [[LHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %2
; CHECK: [[RHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %3
- ; CHECK: %5(32) = G_ICMP { s32, s32 } intpred(ne), [[LHS32]], [[RHS32]]
- %5(32) = G_ICMP { s32, s8 } intpred(ne), %2, %3
-
- ; CHECK: [[LHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %2
- ; CHECK: [[RHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %3
- ; CHECK: %6(32) = G_ICMP { s32, s32 } intpred(ugt), [[LHS32]], [[RHS32]]
- %6(32) = G_ICMP { s32, s8 } intpred(ugt), %2, %3
-
- ; CHECK: [[LHS32:%[0-9]+]](32) = G_SEXT { s32, s8 } %2
- ; CHECK: [[RHS32:%[0-9]+]](32) = G_SEXT { s32, s8 } %3
- ; CHECK: %7(32) = G_ICMP { s32, s32 } intpred(sle), [[LHS32]], [[RHS32]]
- %7(32) = G_ICMP { s32, s8 } intpred(sle), %2, %3
-
- ; CHECK: [[LHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %2
- ; CHECK: [[RHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %3
- ; CHECK: [[TST32:%[0-9]+]](32) = G_ICMP { s32, s32 } intpred(ult), [[LHS32]], [[RHS32]]
- ; CHECK: %8(1) = G_TRUNC { s1, s32 } [[TST32]]
+ ; CHECK: %8(1) = G_ICMP { s1, s32 } intpred(ult), [[LHS32]], [[RHS32]]
%8(1) = G_ICMP { s1, s8 } intpred(ult), %2, %3
...
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