[PATCH] D23888: AMDGPU: Remove register operand from si_mask_branch

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm.

It isn't used for anything, and is also misleading since
it could be spilled at the end of the block, so it can't be relied
on. There ends up being a verifier error about using an undefined
register since the spill kills the register.

https://reviews.llvm.org/D23888

Files:
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SILowerControlFlow.cpp

Index: lib/Target/AMDGPU/SILowerControlFlow.cpp
===================================================================
--- lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -136,8 +136,7 @@
   // be used later when inserting skips.
   MachineInstr *NewBr =
     BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
-    .addOperand(MI.getOperand(2))
-    .addReg(SaveExecReg, getKillRegState(SaveExec.isKill()));
+    .addOperand(MI.getOperand(2));
 
   if (!LIS) {
     MI.eraseFromParent();
@@ -196,8 +195,7 @@
   // Insert a pseudo terminator to help keep the verifier happy.
   MachineInstr *Branch =
     BuildMI(MBB, Term, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
-    .addMBB(DestBB)
-    .addReg(DstReg);
+    .addMBB(DestBB);
 
   if (!LIS) {
     MI.eraseFromParent();
Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -1802,7 +1802,7 @@
 // Dummy terminator instruction to use after control flow instructions
 // replaced with exec mask operations.
 def SI_MASK_BRANCH : PseudoInstSI <
-  (outs), (ins brtarget:$target, SReg_64:$dst)> {
+  (outs), (ins brtarget:$target)> {
   let isBranch = 0;
   let isTerminator = 1;
   let isBarrier = 0;


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