[llvm] r279680 - MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 24 15:34:06 PDT 2016
Author: matze
Date: Wed Aug 24 17:34:06 2016
New Revision: 279680
URL: http://llvm.org/viewvc/llvm-project?rev=279680&view=rev
Log:
MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it
Modified:
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir
llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir
llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Wed Aug 24 17:34:06 2016
@@ -281,14 +281,6 @@ void MIRParserImpl::createDummyFunction(
new UnreachableInst(Context, BB);
}
-static bool hasPHI(const MachineFunction &MF) {
- for (const MachineBasicBlock &MBB : MF)
- for (const MachineInstr &MI : MBB)
- if (MI.isPHI())
- return true;
- return false;
-}
-
static bool isSSA(const MachineFunction &MF) {
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
@@ -301,8 +293,20 @@ static bool isSSA(const MachineFunction
void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
MachineFunctionProperties &Properties = MF.getProperties();
- if (!hasPHI(MF))
+
+ bool HasPHI = false;
+ bool HasInlineAsm = false;
+ for (const MachineBasicBlock &MBB : MF) {
+ for (const MachineInstr &MI : MBB) {
+ if (MI.isPHI())
+ HasPHI = true;
+ if (MI.isInlineAsm())
+ HasInlineAsm = true;
+ }
+ }
+ if (!HasPHI)
Properties.set(MachineFunctionProperties::Property::NoPHIs);
+ MF.setHasInlineAsm(HasInlineAsm);
if (isSSA(MF))
Properties.set(MachineFunctionProperties::Property::IsSSA);
@@ -320,7 +324,6 @@ bool MIRParserImpl::initializeMachineFun
if (YamlMF.Alignment)
MF.setAlignment(YamlMF.Alignment);
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
- MF.setHasInlineAsm(YamlMF.HasInlineAsm);
if (YamlMF.AllVRegsAllocated)
MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Wed Aug 24 17:34:06 2016
@@ -174,7 +174,6 @@ void MIRPrinter::print(const MachineFunc
YamlMF.Name = MF.getName();
YamlMF.Alignment = MF.getAlignment();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
- YamlMF.HasInlineAsm = MF.hasInlineAsm();
YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::AllVRegsAllocated);
Modified: llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir Wed Aug 24 17:34:06 2016
@@ -28,7 +28,6 @@
name: promote-load-from-store
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
liveins:
@@ -84,7 +83,6 @@ body: |
name: store-pair
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
liveins:
Modified: llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir Wed Aug 24 17:34:06 2016
@@ -15,7 +15,6 @@
name: test_mov_0
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
frameInfo:
Modified: llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir Wed Aug 24 17:34:06 2016
@@ -79,7 +79,6 @@
name: f
alignment: 1
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
liveins:
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir Wed Aug 24 17:34:06 2016
@@ -33,7 +33,6 @@
name: test_tlsdesc_callseq_length
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
liveins:
Modified: llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir Wed Aug 24 17:34:06 2016
@@ -90,7 +90,6 @@
name: f
alignment: 1
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
liveins:
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir Wed Aug 24 17:34:06 2016
@@ -24,7 +24,6 @@
# CHECK: name: foo
# CHECK-NEXT: alignment:
# CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
# CHECK: ...
name: foo
body: |
@@ -34,7 +33,6 @@ body: |
# CHECK: name: bar
# CHECK-NEXT: alignment:
# CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
# CHECK: ...
name: bar
body: |
@@ -44,7 +42,6 @@ body: |
# CHECK: name: func
# CHECK-NEXT: alignment: 8
# CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
# CHECK: ...
name: func
alignment: 8
@@ -55,12 +52,10 @@ body: |
# CHECK: name: func2
# CHECK-NEXT: alignment: 16
# CHECK-NEXT: exposesReturnsTwice: true
-# CHECK-NEXT: hasInlineAsm: true
# CHECK: ...
name: func2
alignment: 16
exposesReturnsTwice: true
-hasInlineAsm: true
body: |
bb.0:
...
Modified: llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir Wed Aug 24 17:34:06 2016
@@ -175,7 +175,6 @@
name: test0a
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -221,7 +220,6 @@ body: |
name: test0b
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -265,7 +263,6 @@ body: |
name: test1a
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -313,7 +310,6 @@ body: |
name: test1b
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -361,7 +357,6 @@ body: |
name: test2a
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -409,7 +404,6 @@ body: |
name: test2b
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -457,7 +451,6 @@ body: |
name: test3
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -505,7 +498,6 @@ body: |
name: test4
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
@@ -617,7 +609,6 @@ body: |
name: testBB
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
Modified: llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir Wed Aug 24 17:34:06 2016
@@ -10,7 +10,6 @@
...
---
name: test
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
Modified: llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir Wed Aug 24 17:34:06 2016
@@ -19,7 +19,6 @@
...
---
name: test
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir Wed Aug 24 17:34:06 2016
@@ -10,7 +10,6 @@
...
---
name: test
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir Wed Aug 24 17:34:06 2016
@@ -10,7 +10,6 @@
...
---
name: test
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
Modified: llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir Wed Aug 24 17:34:06 2016
@@ -19,7 +19,6 @@
...
---
name: test
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
@@ -36,7 +35,6 @@ body: |
...
---
name: test2
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir Wed Aug 24 17:34:06 2016
@@ -10,7 +10,6 @@
...
---
name: test
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
Modified: llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir Wed Aug 24 17:34:06 2016
@@ -10,7 +10,6 @@
...
---
name: test
-hasInlineAsm: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
Modified: llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir Wed Aug 24 17:34:06 2016
@@ -44,7 +44,6 @@
name: mm_update_next_owner
alignment: 4
exposesReturnsTwice: false
-hasInlineAsm: true
allVRegsAllocated: true
tracksRegLiveness: true
liveins:
Modified: llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir Wed Aug 24 17:34:06 2016
@@ -26,7 +26,6 @@
name: test1
alignment: 4
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
frameInfo:
Modified: llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir Wed Aug 24 17:34:06 2016
@@ -39,7 +39,6 @@
name: main
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0 }
Modified: llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir Wed Aug 24 17:34:06 2016
@@ -32,7 +32,6 @@
name: fn1
alignment: 2
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
registers:
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir Wed Aug 24 17:34:06 2016
@@ -157,7 +157,6 @@
name: add
alignment: 4
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
liveins:
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279680&r1=279679&r2=279680&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir Wed Aug 24 17:34:06 2016
@@ -159,7 +159,6 @@
name: main
alignment: 4
exposesReturnsTwice: false
-hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
liveins:
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