[llvm] r279629 - AMDGPU : Add V_SAD_U32 instruction pattern.
Wei Ding via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 24 07:59:47 PDT 2016
Author: wdng
Date: Wed Aug 24 09:59:47 2016
New Revision: 279629
URL: http://llvm.org/viewvc/llvm-project?rev=279629&view=rev
Log:
AMDGPU : Add V_SAD_U32 instruction pattern.
Differential Revision: http://reviews.llvm.org/D23069
Added:
llvm/trunk/test/CodeGen/AMDGPU/sad.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=279629&r1=279628&r2=279629&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Wed Aug 24 09:59:47 2016
@@ -172,6 +172,12 @@ class HasOneUseBinOp<SDPatternOperator o
[{ return N->hasOneUse(); }]
>;
+class HasOneUseTernaryOp<SDPatternOperator op> : PatFrag<
+ (ops node:$src0, node:$src1, node:$src2),
+ (op $src0, $src1, $src2),
+ [{ return N->hasOneUse(); }]
+>;
+
//===----------------------------------------------------------------------===//
// Load/Store Pattern Fragments
//===----------------------------------------------------------------------===//
@@ -618,8 +624,10 @@ def smax_oneuse : HasOneUseBinOp<smax>;
def smin_oneuse : HasOneUseBinOp<smin>;
def umax_oneuse : HasOneUseBinOp<umax>;
def umin_oneuse : HasOneUseBinOp<umin>;
+def sub_oneuse : HasOneUseBinOp<sub>;
} // Properties = [SDNPCommutative, SDNPAssociative]
+def select_oneuse : HasOneUseTernaryOp<select>;
// 24-bit arithmetic patterns
def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=279629&r1=279628&r2=279629&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Wed Aug 24 09:59:47 2016
@@ -3309,6 +3309,25 @@ defm : SI_INDIRECT_Pattern <v8i32, i32,
defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">;
//===----------------------------------------------------------------------===//
+// SAD Patterns
+//===----------------------------------------------------------------------===//
+
+def : Pat <
+ (add (sub_oneuse (umax i32:$src0, i32:$src1),
+ (umin i32:$src0, i32:$src1)),
+ i32:$src2),
+ (V_SAD_U32 $src0, $src1, $src2)
+>;
+
+def : Pat <
+ (add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
+ (sub i32:$src0, i32:$src1),
+ (sub i32:$src1, i32:$src0)),
+ i32:$src2),
+ (V_SAD_U32 $src0, $src1, $src2)
+>;
+
+//===----------------------------------------------------------------------===//
// Conversion Patterns
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/CodeGen/AMDGPU/sad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sad.ll?rev=279629&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/sad.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/sad.ll Wed Aug 24 09:59:47 2016
@@ -0,0 +1,283 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}v_sad_u32_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %t0 = select i1 %icmp0, i32 %a, i32 %b
+
+ %icmp1 = icmp ule i32 %a, %b
+ %t1 = select i1 %icmp1, i32 %a, i32 %b
+
+ %ret0 = sub i32 %t0, %t1
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_constant_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 20
+define void @v_sad_u32_constant_pat1(i32 addrspace(1)* %out, i32 %a) {
+ %icmp0 = icmp ugt i32 %a, 90
+ %t0 = select i1 %icmp0, i32 %a, i32 90
+
+ %icmp1 = icmp ule i32 %a, 90
+ %t1 = select i1 %icmp1, i32 %a, i32 90
+
+ %ret0 = sub i32 %t0, %t1
+ %ret = add i32 %ret0, 20
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_pat2:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %sub0 = sub i32 %a, %b
+ %sub1 = sub i32 %b, %a
+ %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
+
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat1:
+; GCN: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: s_min_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+define void @v_sad_u32_multi_use_sub_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %t0 = select i1 %icmp0, i32 %a, i32 %b
+
+ %icmp1 = icmp ule i32 %a, %b
+ %t1 = select i1 %icmp1, i32 %a, i32 %b
+
+ %ret0 = sub i32 %t0, %t1
+ store volatile i32 %ret0, i32 *undef
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_multi_use_add_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_multi_use_add_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %t0 = select i1 %icmp0, i32 %a, i32 %b
+
+ %icmp1 = icmp ule i32 %a, %b
+ %t1 = select i1 %icmp1, i32 %a, i32 %b
+
+ %ret0 = sub i32 %t0, %t1
+ %ret = add i32 %ret0, %c
+ store volatile i32 %ret, i32 *undef
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_multi_use_max_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_multi_use_max_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %t0 = select i1 %icmp0, i32 %a, i32 %b
+ store volatile i32 %t0, i32 *undef
+
+ %icmp1 = icmp ule i32 %a, %b
+ %t1 = select i1 %icmp1, i32 %a, i32 %b
+
+ %ret0 = sub i32 %t0, %t1
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_multi_use_min_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_multi_use_min_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %t0 = select i1 %icmp0, i32 %a, i32 %b
+
+ %icmp1 = icmp ule i32 %a, %b
+ %t1 = select i1 %icmp1, i32 %a, i32 %b
+
+ store volatile i32 %t1, i32 *undef
+
+ %ret0 = sub i32 %t0, %t1
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat2:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %sub0 = sub i32 %a, %b
+ store volatile i32 %sub0, i32 *undef
+ %sub1 = sub i32 %b, %a
+ %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
+
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2:
+; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: v_cmp_gt_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %sub0 = sub i32 %a, %b
+ %sub1 = sub i32 %b, %a
+ %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
+ store volatile i32 %ret0, i32 *undef
+
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_vector_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_vector_pat1(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+ %icmp0 = icmp ugt <4 x i32> %a, %b
+ %t0 = select <4 x i1> %icmp0, <4 x i32> %a, <4 x i32> %b
+
+ %icmp1 = icmp ule <4 x i32> %a, %b
+ %t1 = select <4 x i1> %icmp1, <4 x i32> %a, <4 x i32> %b
+
+ %ret0 = sub <4 x i32> %t0, %t1
+ %ret = add <4 x i32> %ret0, %c
+
+ store <4 x i32> %ret, <4 x i32> addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_vector_pat2:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_vector_pat2(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+ %icmp0 = icmp ugt <4 x i32> %a, %b
+ %sub0 = sub <4 x i32> %a, %b
+ %sub1 = sub <4 x i32> %b, %a
+ %ret0 = select <4 x i1> %icmp0, <4 x i32> %sub0, <4 x i32> %sub1
+
+ %ret = add <4 x i32> %ret0, %c
+
+ store <4 x i32> %ret, <4 x i32> addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_i16_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_i16_pat1(i16 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
+
+ %icmp0 = icmp ugt i16 %a, %b
+ %t0 = select i1 %icmp0, i16 %a, i16 %b
+
+ %icmp1 = icmp ule i16 %a, %b
+ %t1 = select i1 %icmp1, i16 %a, i16 %b
+
+ %ret0 = sub i16 %t0, %t1
+ %ret = add i16 %ret0, %c
+
+ store i16 %ret, i16 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_i16_pat2:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_i16_pat2(i16 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b, i16 zeroext %c) {
+ %icmp0 = icmp ugt i16 %a, %b
+ %sub0 = sub i16 %a, %b
+ %sub1 = sub i16 %b, %a
+ %ret0 = select i1 %icmp0, i16 %sub0, i16 %sub1
+
+ %ret = add i16 %ret0, %c
+
+ store i16 %ret, i16 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_i8_pat1:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_i8_pat1(i8 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
+ %icmp0 = icmp ugt i8 %a, %b
+ %t0 = select i1 %icmp0, i8 %a, i8 %b
+
+ %icmp1 = icmp ule i8 %a, %b
+ %t1 = select i1 %icmp1, i8 %a, i8 %b
+
+ %ret0 = sub i8 %t0, %t1
+ %ret = add i8 %ret0, %c
+
+ store i8 %ret, i8 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_i8_pat2:
+; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_i8_pat2(i8 addrspace(1)* %out, i8 zeroext %a, i8 zeroext %b, i8 zeroext %c) {
+ %icmp0 = icmp ugt i8 %a, %b
+ %sub0 = sub i8 %a, %b
+ %sub1 = sub i8 %b, %a
+ %ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1
+
+ %ret = add i8 %ret0, %c
+
+ store i8 %ret, i8 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat1:
+; GCN: v_cmp_le_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}
+; GCN: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_mismatched_operands_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %t0 = select i1 %icmp0, i32 %a, i32 %b
+
+ %icmp1 = icmp ule i32 %a, %b
+ %t1 = select i1 %icmp1, i32 %a, i32 %d
+
+ %ret0 = sub i32 %t0, %t1
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat2:
+; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
+define void @v_sad_u32_mismatched_operands_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
+ %icmp0 = icmp ugt i32 %a, %b
+ %sub0 = sub i32 %a, %d
+ %sub1 = sub i32 %b, %a
+ %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
+
+ %ret = add i32 %ret0, %c
+
+ store i32 %ret, i32 addrspace(1)* %out
+ ret void
+}
+
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