[llvm] r279604 - TargetSchedule: Do not consider subregister definitions as reads.

[Matthias Braun via llvm-commits]

Author: matze
Date: Tue Aug 23 21:32:29 2016
New Revision: 279604

URL: http://llvm.org/viewvc/llvm-project?rev=279604&view=rev
Log:
TargetSchedule: Do not consider subregister definitions as reads.

We should not consider subregister definitions as reads for schedule
model purposes (they are just modeled as reads of the overal vreg for
liveness calculation purposes, the CPU instructions are not actually
reading).

Unfortunately I cannot submit a test for this as it requires a target
which uses ReadAdvance annotation in the scheduling model and has
subregister liveness enabled at the same time, which is only the case on
an out of tree target.

Modified:
    llvm/trunk/lib/CodeGen/TargetSchedule.cpp

Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=279604&r1=279603&r2=279604&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Tue Aug 23 21:32:29 2016
@@ -144,7 +144,7 @@ static unsigned findUseIdx(const Machine
   unsigned UseIdx = 0;
   for (unsigned i = 0; i != UseOperIdx; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.readsReg())
+    if (MO.isReg() && MO.readsReg() && !MO.isDef())
       ++UseIdx;
   }
   return UseIdx;