[PATCH] D22722: MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL279600: MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. (authored by matze).

Changed prior to commit:
  https://reviews.llvm.org/D22722?vs=65213&id=69068#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D22722

Files:
  llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
  llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
  llvm/trunk/lib/CodeGen/MIRPrinter.cpp
  llvm/trunk/lib/CodeGen/MachineVerifier.cpp
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-property.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
  llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
  llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
  llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
  llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
  llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
  llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
  llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
  llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir
  llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
  llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
  llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir
  llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir
  llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
  llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
  llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
  llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
  llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
  llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
  llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
  llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir
  llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir
  llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir
  llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
  llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir
  llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir
  llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
  llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir
  llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir
  llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir
  llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
  llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
  llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir
  llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir
  llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir
  llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
  llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
  llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir
  llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
  llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
  llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
  llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir
  llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
  llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
  llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
  llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
  llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
  llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir
  llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
  llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
  llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir

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