[PATCH] D23677: [AArch64] Avoid materializing constant values when generating csel/csinv/csinc instructions.

[Eli Friedman via llvm-commits]

efriedma added a comment.

Possibly interesting testcase: "x == 7 ? 7 : -1".  Should generate cmp+csinv.  Also, the related "x == 7 ? 7 : 1" should generate cmp+csinc.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:4003
@@ +4002,3 @@
+        else {
+          // If FVal is -1, we can use a CSINV to invert wzr/xzr to potentially
+          // avoid materializing the -1.
----------------
Maybe you could just make this fall through to the general case, rather than explicitly selecting CSINV?

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:4015
@@ -4004,3 +4014,3 @@
         // an overflow (which would not be the case if we do the check with
         // 64-bit arithmetic).
         const uint32_t TrueVal32 = CTVal->getZExtValue();
----------------
Maybe it makes sense to write something more like `if ((TrueVal == SignExtend64(FalseVal + 1, ValueBits)) || (SignExtend64(TrueVal + 1, ValueBits) == FalseVal)) {`.  This also applies to your later code.


https://reviews.llvm.org/D23677