[llvm] r279565 - GlobalISel: legalize conditional branches on AArch64.

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Tue Aug 23 16:01:20 2016
New Revision: 279565

URL: http://llvm.org/viewvc/llvm-project?rev=279565&view=rev
Log:
GlobalISel: legalize conditional branches on AArch64.

Modified:
    llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
    llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
    llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=279565&r1=279564&r2=279565&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Tue Aug 23 16:01:20 2016
@@ -169,7 +169,8 @@ public:
   ///
   /// G_BRCOND is a conditional branch to \p Dest. At the beginning of
   /// legalization, \p Ty will be a single bit (s1). Targets with interesting
-  /// flags registers may change this.
+  /// flags registers may change this. For a wider type, whether the branch is
+  /// taken must only depend on bit 0 (for now).
   ///
   /// \pre setBasicBlock or setMI must have been called.
   ///

Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp?rev=279565&r1=279564&r2=279565&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp Tue Aug 23 16:01:20 2016
@@ -173,6 +173,13 @@ MachineLegalizeHelper::widenScalar(Machi
     MI.eraseFromParent();
     return Legalized;
   }
+  case TargetOpcode::G_BRCOND: {
+    unsigned TstExt = MRI.createGenericVirtualRegister(WideSize);
+    MIRBuilder.buildAnyExtend(WideTy, TstExt, MI.getOperand(0).getReg());
+    MIRBuilder.buildBrCond(WideTy, TstExt, *MI.getOperand(1).getMBB());
+    MI.eraseFromParent();
+    return Legalized;
+  }
   }
 }
 

Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp?rev=279565&r1=279564&r2=279565&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineLegalizer.cpp Tue Aug 23 16:01:20 2016
@@ -30,7 +30,12 @@ MachineLegalizer::MachineLegalizer() : T
   DefaultActions[TargetOpcode::G_ANYEXTEND] = Legal;
   DefaultActions[TargetOpcode::G_TRUNC] = Legal;
 
+  DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
+  DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
+
   DefaultActions[TargetOpcode::G_ADD] = NarrowScalar;
+
+  DefaultActions[TargetOpcode::G_BRCOND] = WidenScalar;
 }
 
 void MachineLegalizer::computeTables() {

Modified: llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp?rev=279565&r1=279564&r2=279565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MachineLegalizer.cpp Tue Aug 23 16:01:20 2016
@@ -62,6 +62,7 @@ AArch64MachineLegalizer::AArch64MachineL
     setAction({MemOp, 1, p0}, Legal);
   }
 
+  // Constants
   for (auto Ty : {s32, s64}) {
     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
     setAction({TargetOpcode::G_FCONSTANT, Ty}, Legal);
@@ -72,8 +73,13 @@ AArch64MachineLegalizer::AArch64MachineL
 
   setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar);
 
+  // Control-flow
   setAction({G_BR, LLT::unsized()}, Legal);
+  setAction({G_BRCOND, s32}, Legal);
+  for (auto Ty : {s1, s8, s16})
+    setAction({G_BRCOND, Ty}, WidenScalar);
 
+  // Pointer-handling
   setAction({G_FRAME_INDEX, p0}, Legal);
 
   setAction({G_PTRTOINT, 0, s64}, Legal);

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir?rev=279565&r1=279564&r2=279565&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir Tue Aug 23 16:01:20 2016
@@ -6,6 +6,8 @@
   define void @test_simple() {
   entry:
     ret void
+  next:
+    ret void
   }
 ...
 
@@ -16,6 +18,7 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
+  - { id: 3, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
@@ -26,4 +29,11 @@ body: |
     ; CHECK: %2(64) = G_INTTOPTR { p0, s64 } %1
     %1(64) = G_PTRTOINT { s64, p0 } %0
     %2(64) = G_INTTOPTR { p0, s64 } %1
+
+    ; CHECK: [[TST32:%[0-9]+]](32) = G_ANYEXTEND s32 %3
+    ; CHECK: G_BRCOND s32 [[TST32]], %bb.1.next
+    %3(1) = G_TRUNC { s1, s64 } %0
+    G_BRCOND s1 %3, %bb.1.next
+
+  bb.1.next:
 ...