[PATCH] D21982: [compiler-rt][XRay] Initial per-thread inmemory logging implementation

[Dean Michael Berris via llvm-commits]

dberris planned changes to this revision.

================
Comment at: include/xray/xray_records.h:48
@@ +47,3 @@
+} __attribute__((packed));
+
+static_assert(sizeof(XRayFileHeader) == 32, "XRayFileHeader != 32 bytes");
----------------
sdardis wrote:
> Apologies for the drive-by comment.
> 
> Pre MIPSR6 requires different instructions (e.g. swl/swr to store 4 bytes) to write unaligned data if it is not naturally aligned to its size. Attempting to access 2/4/8 byte words with a normal load/store triggers a CPU level address exception if unaligned.
> 
> For MIPSR6 unaligned support is required, but it is implementation dependent how this is achieved. For example, an implementation could support unaligned access within a cacheline but require OS intervention if the unaligned access crosses a cacheline.
> 
> IIRC x86, PowerPC, AArch64 have native support for unaligned access. SPARC, ARM typically don't.
> Apologies for the drive-by comment.

No need for apologies, comments most appreciated!

> Pre MIPSR6 requires different instructions (e.g. swl/swr to store 4 bytes) to write unaligned data if it is not naturally aligned to its size. Attempting to access 2/4/8 byte words with a normal load/store triggers a CPU level address exception if unaligned.
>
> For MIPSR6 unaligned support is required, but it is implementation dependent how this is achieved. For example, an implementation could support unaligned access within a cacheline but require OS intervention if the unaligned access crosses a cacheline.
>
> IIRC x86, PowerPC, AArch64 have native support for unaligned access. SPARC, ARM typically don't.

Cool, this is good to know. Happy to change this implementation to be more portable to more platforms. :)


https://reviews.llvm.org/D21982