[llvm] r279508 - [X86][SSE] Demonstrate inability to recognise that (v)cvtpd2ps implicitly zeroes the upper half of the xmm

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Aug 23 05:35:24 2016
New Revision: 279508

URL: http://llvm.org/viewvc/llvm-project?rev=279508&view=rev
Log:
[X86][SSE] Demonstrate inability to recognise that (v)cvtpd2ps implicitly zeroes the upper half of the xmm

Modified:
    llvm/trunk/test/CodeGen/X86/vec_fptrunc.ll

Modified: llvm/trunk/test/CodeGen/X86/vec_fptrunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_fptrunc.ll?rev=279508&r1=279507&r2=279508&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_fptrunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_fptrunc.ll Tue Aug 23 05:35:24 2016
@@ -133,6 +133,67 @@ entry:
   ret void
 }
 
+define <4 x float> @fptrunc_frommem2_zext(<2 x double> * %ld) {
+; X32-SSE-LABEL: fptrunc_frommem2_zext:
+; X32-SSE:       # BB#0:
+; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-SSE-NEXT:    cvtpd2ps (%eax), %xmm0
+; X32-SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; X32-SSE-NEXT:    retl
+;
+; X32-AVX-LABEL: fptrunc_frommem2_zext:
+; X32-AVX:       # BB#0:
+; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-AVX-NEXT:    vcvtpd2psx (%eax), %xmm0
+; X32-AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; X32-AVX-NEXT:    retl
+;
+; X64-SSE-LABEL: fptrunc_frommem2_zext:
+; X64-SSE:       # BB#0:
+; X64-SSE-NEXT:    cvtpd2ps (%rdi), %xmm0
+; X64-SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; X64-SSE-NEXT:    retq
+;
+; X64-AVX-LABEL: fptrunc_frommem2_zext:
+; X64-AVX:       # BB#0:
+; X64-AVX-NEXT:    vcvtpd2psx (%rdi), %xmm0
+; X64-AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; X64-AVX-NEXT:    retq
+  %arg = load <2 x double>, <2 x double> * %ld, align 16
+  %cvt = fptrunc <2 x double> %arg to <2 x float>
+  %ret = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
+  ret <4 x float> %ret
+}
+
+define <4 x float> @fptrunc_fromreg2_zext(<2 x double> %arg) {
+; X32-SSE-LABEL: fptrunc_fromreg2_zext:
+; X32-SSE:       # BB#0:
+; X32-SSE-NEXT:    cvtpd2ps %xmm0, %xmm0
+; X32-SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; X32-SSE-NEXT:    retl
+;
+; X32-AVX-LABEL: fptrunc_fromreg2_zext:
+; X32-AVX:       # BB#0:
+; X32-AVX-NEXT:    vcvtpd2ps %xmm0, %xmm0
+; X32-AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; X32-AVX-NEXT:    retl
+;
+; X64-SSE-LABEL: fptrunc_fromreg2_zext:
+; X64-SSE:       # BB#0:
+; X64-SSE-NEXT:    cvtpd2ps %xmm0, %xmm0
+; X64-SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; X64-SSE-NEXT:    retq
+;
+; X64-AVX-LABEL: fptrunc_fromreg2_zext:
+; X64-AVX:       # BB#0:
+; X64-AVX-NEXT:    vcvtpd2ps %xmm0, %xmm0
+; X64-AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; X64-AVX-NEXT:    retq
+  %cvt = fptrunc <2 x double> %arg to <2 x float>
+  %ret = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
+  ret <4 x float> %ret
+}
+
 ; FIXME: For exact truncations we should be able to fold this.
 define <4 x float> @fptrunc_fromconst() {
 ; X32-SSE-LABEL: fptrunc_fromconst: