[PATCH] D23764: Remove MVT:i1 xor instruction before SELECT. (Performance improvement).

[Ayman Musa via llvm-commits]

aymanmus created this revision.
aymanmus added reviewers: hfinkel, MatzeB.
aymanmus added a subscriber: llvm-commits.
Herald added a subscriber: nemanjai.

Fold the two following sequences:
Sequence 1 (xor with 0):
%cond1 = xor i1:%cond0 Constant<i1>0
%res = select %cond1, m, n
into:
%res = select %cond0,** m, n**

Sequence 2 (xor with 1):
%cond1 = xor i1:%cond0 Constant<i1>1
%res = select %cond1, m, n
into:
%res = select %cond0,** n, m**



https://reviews.llvm.org/D23764

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/PowerPC/select-i1-vs-i1.ll

Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5238,6 +5238,22 @@
     }
   }
 
+  // select (xor Cond, 1), X, Y -> select Cond, Y, X
+  // select (xor Cond, 0), X, Y -> selext Cond, X, Y
+  if (VT0 == MVT::i1) {
+    if (N0->getOpcode() == ISD::XOR && N0->hasOneUse()) {
+      if(auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) {
+        SDValue Cond0 = N0->getOperand(0);
+        if (C->getAPIntValue() == 1) 
+          return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), 
+                             Cond0, N2, N1);
+        else
+          return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), 
+                             Cond0, N1, N2);
+      }
+    }
+  }
+
   // fold selects based on a setcc into other things, such as min/max/abs
   if (N0.getOpcode() == ISD::SETCC) {
     // select x, y (fcmp lt x, y) -> fminnum x, y
Index: test/CodeGen/PowerPC/select-i1-vs-i1.ll
===================================================================
--- test/CodeGen/PowerPC/select-i1-vs-i1.ll
+++ test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -800,10 +800,10 @@
 ; CHECK-LABEL: @testv4floateq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
-; CHECK-DAG: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 35, 35
+; CHECK-DAG: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: xxlor [[REG2]], 34, 34
 ; CHECK: .LBB[[BB]]:
 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
 ; CHECK: blr
@@ -928,15 +928,15 @@
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3
 ; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: creqv [[REG3:[0-9]+]], [[REG2]], [[REG1]]
+; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]]
 ; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
-; CHECK: fmr 9, 11
+; CHECK: fmr 11, 9
 ; CHECK: .LBB[[BB1]]:
 ; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
-; CHECK: fmr 10, 12
+; CHECK: fmr 12, 10
 ; CHECK: .LBB[[BB2]]:
-; CHECK-DAG: fmr 1, 9
-; CHECK-DAG: fmr 2, 10
+; CHECK-DAG: fmr 1, 11
+; CHECK-DAG: fmr 2, 12
 ; CHECK: blr
 }
 
@@ -1019,9 +1019,11 @@
 ; CHECK-LABEL: @testv2doubleeq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]]
+; CHECK: vor 3, 2, 2
+; CHECK: .LBB[[BB55]]
+; CHECK: xxlor 34, 35, 35
 ; CHECK: blr
 }
 


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