[llvm] r279409 - Reformat.
NAKAMURA Takumi via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 21 17:58:47 PDT 2016
Author: chapuni
Date: Sun Aug 21 19:58:47 2016
New Revision: 279409
URL: http://llvm.org/viewvc/llvm-project?rev=279409&view=rev
Log:
Reformat.
Modified:
llvm/trunk/lib/Object/MachOObjectFile.cpp
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=279409&r1=279408&r2=279409&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Sun Aug 21 19:58:47 2016
@@ -235,7 +235,7 @@ static Error parseSegmentLoadCommand(
if (S.nsects > std::numeric_limits<uint32_t>::max() / SectionSize ||
S.nsects * SectionSize > Load.C.cmdsize - SegmentLoadSize)
return malformedError("load command " + Twine(LoadCommandIndex) +
- " inconsistent cmdsize in " + CmdName +
+ " inconsistent cmdsize in " + CmdName +
" for the number of sections");
for (unsigned J = 0; J < S.nsects; ++J) {
const char *Sec = getSectionPtr(Obj, Load, J);
@@ -309,7 +309,7 @@ static Error parseSegmentLoadCommand(
}
if (S.fileoff > FileSize)
return malformedError("load command " + Twine(LoadCommandIndex) +
- " fileoff field in " + CmdName +
+ " fileoff field in " + CmdName +
" extends past the end of the file");
uint64_t BigSize = S.fileoff;
BigSize += S.filesize;
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=279409&r1=279408&r2=279409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Sun Aug 21 19:58:47 2016
@@ -458,7 +458,7 @@ void PPCFastISel::PPCSimplifyAddress(Add
// Emit a load instruction if possible, returning true if we succeeded,
// otherwise false. See commentary below for how the register class of
-// the load is determined.
+// the load is determined.
bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
const TargetRegisterClass *RC,
bool IsZExt, unsigned FP64LoadOpc) {
@@ -489,20 +489,18 @@ bool PPCFastISel::PPCEmitLoad(MVT VT, un
Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
break;
case MVT::i16:
- Opc = (IsZExt ?
- (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
- (Is32BitInt ? PPC::LHA : PPC::LHA8));
+ Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
+ : (Is32BitInt ? PPC::LHA : PPC::LHA8));
break;
case MVT::i32:
- Opc = (IsZExt ?
- (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
- (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
+ Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
+ : (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
UseOffset = false;
break;
case MVT::i64:
Opc = PPC::LD;
- assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
+ assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
"64-bit load with 32-bit target??");
UseOffset = ((Addr.Offset & 3) == 0);
break;
@@ -699,8 +697,9 @@ bool PPCFastISel::PPCEmitStore(MVT VT, u
// Base reg with offset in range.
} else if (UseOffset) {
// VSX only provides an indexed store.
- if (Is32VSXStore || Is64VSXStore) return false;
-
+ if (Is32VSXStore || Is64VSXStore)
+ return false;
+
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
.addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
@@ -838,7 +837,7 @@ bool PPCFastISel::PPCEmitCmp(const Value
long Imm = 0;
bool UseImm = false;
- // Only 16-bit integer constants can be represented in compares for
+ // Only 16-bit integer constants can be represented in compares for
// PowerPC. Others will be materialized into a register.
if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
@@ -1627,7 +1626,7 @@ bool PPCFastISel::SelectRet(const Instru
CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
const Value *RV = Ret->getOperand(0);
-
+
// FIXME: Only one output register for now.
if (ValLocs.size() > 1)
return false;
@@ -1673,7 +1672,7 @@ bool PPCFastISel::SelectRet(const Instru
if (RVVT != DestVT && RVVT != MVT::i8 &&
RVVT != MVT::i16 && RVVT != MVT::i32)
return false;
-
+
if (RVVT != DestVT) {
switch (VA.getLocInfo()) {
default:
@@ -1948,8 +1947,9 @@ unsigned PPCFastISel::PPCMaterializeFP(c
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
- .addImm(0).addReg(TmpReg2);
- } else
+ .addImm(0)
+ .addReg(TmpReg2);
+ } else
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
.addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
.addReg(TmpReg)
@@ -2040,8 +2040,8 @@ unsigned PPCFastISel::PPCMaterialize32Bi
// Just Hi bits.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
- .addImm(Hi);
-
+ .addImm(Hi);
+
return ResultReg;
}
@@ -2275,7 +2275,7 @@ bool PPCFastISel::fastLowerArguments() {
// Handle materializing integer constants into a register. This is not
// automatically generated for PowerPC, so must be explicitly created here.
unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
-
+
if (Opc != ISD::Constant)
return 0;
@@ -2288,8 +2288,8 @@ unsigned PPCFastISel::fastEmit_i(MVT Ty,
return ImmReg;
}
- if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
- VT != MVT::i8 && VT != MVT::i1)
+ if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
+ VT != MVT::i1)
return 0;
const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
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