[PATCH] D23677: [AArch64] Avoid materializing -1 values when generating csinv instructions.

[Chad Rosier via llvm-commits]

mcrosier marked 2 inline comments as done.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:4001
@@ +4000,3 @@
+      } else if (CFVal->isAllOnesValue() && RHSVal == CTVal &&
+                 changeIntCCToAArch64CC(CC) == AArch64CC::EQ) {
+        // If FVal is -1, we can use a CSINV to invert wzr/xzr to avoid
----------------
efriedma wrote:
> There are really two transformations going on here...
> 
> 1. You can avoid materializing -1 using CSINV on the zero register.  (Similarly, you can avoid materializing 1 with CSINC on the zero register.)
> 2. You can transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
> 
> We want to perform each of these transformations whether or not the other is possible.
I made the same realization last night.

I've been working on a new patch this morning.  This general transform (#2) is applicable to CSEL, CSNEG, CSINV, etc.  Transform #1 is specific to CSINV and is independent of tranform #2 as you've already pointed out.

I'll post a revised patch shortly.


https://reviews.llvm.org/D23677