[llvm] r279249 - [Hexagon] Check for empty live interval
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 19 07:29:44 PDT 2016
Author: kparzysz
Date: Fri Aug 19 09:29:43 2016
New Revision: 279249
URL: http://llvm.org/viewvc/llvm-project?rev=279249&view=rev
Log:
[Hexagon] Check for empty live interval
Patch by Brendon Cahoon.
Added:
llvm/trunk/test/CodeGen/Hexagon/expand-condsets-undef2.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=279249&r1=279248&r2=279249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Fri Aug 19 09:29:43 2016
@@ -1140,6 +1140,8 @@ bool HexagonExpandCondsets::coalesceRegi
LiveInterval &L1 = LIS->getInterval(R1.Reg);
LiveInterval &L2 = LIS->getInterval(R2.Reg);
+ if (L2.empty())
+ return false;
bool Overlap = L1.overlaps(L2);
DEBUG(dbgs() << "compatible registers: ("
Added: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-undef2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-undef2.ll?rev=279249&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-undef2.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-undef2.ll Fri Aug 19 09:29:43 2016
@@ -0,0 +1,47 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+; Test that the HexagonExpandCondsets pass does not assert due to
+; attempting to shrink a live interval incorrectly.
+
+
+define void @test() #0 {
+entry:
+ br i1 undef, label %cleanup, label %if.end
+
+if.end:
+ %0 = load i32, i32* undef, align 4
+ %sext = shl i32 %0, 16
+ %conv19 = ashr exact i32 %sext, 16
+ br i1 undef, label %cleanup, label %for.body.lr.ph
+
+for.body.lr.ph:
+ br label %for.body
+
+for.body:
+ %bestScoreL16Q4.0278 = phi i16 [ 32767, %for.body.lr.ph ], [ %.sink, %early_termination ]
+ br i1 false, label %for.body44.lr.ph, label %for.cond90.preheader
+
+for.body44.lr.ph:
+ %conv77 = sext i16 %bestScoreL16Q4.0278 to i32
+ unreachable
+
+for.cond90.preheader:
+ br i1 undef, label %early_termination, label %for.body97
+
+for.body97:
+ br i1 undef, label %for.body97, label %early_termination
+
+early_termination:
+ %.sink = select i1 undef, i16 undef, i16 %bestScoreL16Q4.0278
+ %cmp27 = icmp slt i32 undef, %conv19
+ br i1 %cmp27, label %for.body, label %for.end124
+
+for.end124:
+ unreachable
+
+cleanup:
+ ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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