[llvm] r279241 - [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumpr
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 19 07:04:46 PDT 2016
Author: kparzysz
Date: Fri Aug 19 09:04:45 2016
New Revision: 279241
URL: http://llvm.org/viewvc/llvm-project?rev=279241&view=rev
Log:
[Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumpr
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
llvm/trunk/test/CodeGen/Hexagon/block-addr.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=279241&r1=279240&r2=279241&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri Aug 19 09:04:45 2016
@@ -1292,8 +1292,27 @@ bool HexagonInstrInfo::expandPostRAPseud
MI.setDesc(get(Hexagon::J2_jump));
return true;
case Hexagon::PS_tailcall_r:
+ case Hexagon::PS_jmpret:
MI.setDesc(get(Hexagon::J2_jumpr));
return true;
+ case Hexagon::PS_jmprett:
+ MI.setDesc(get(Hexagon::J2_jumprt));
+ return true;
+ case Hexagon::PS_jmpretf:
+ MI.setDesc(get(Hexagon::J2_jumprf));
+ return true;
+ case Hexagon::PS_jmprettnewpt:
+ MI.setDesc(get(Hexagon::J2_jumprtnewpt));
+ return true;
+ case Hexagon::PS_jmpretfnewpt:
+ MI.setDesc(get(Hexagon::J2_jumprfnewpt));
+ return true;
+ case Hexagon::PS_jmprettnew:
+ MI.setDesc(get(Hexagon::J2_jumprtnew));
+ return true;
+ case Hexagon::PS_jmpretfnew:
+ MI.setDesc(get(Hexagon::J2_jumprfnew));
+ return true;
}
return false;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=279241&r1=279240&r2=279241&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Fri Aug 19 09:04:45 2016
@@ -1587,7 +1587,7 @@ let isTerminator = 1, hasSideEffects = 0
defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
- let isReturn = 1, isCodeGenOnly = 1 in
+ let isReturn = 1, isPseudo = 1, isCodeGenOnly = 1 in
defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=279241&r1=279240&r2=279241&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Fri Aug 19 09:04:45 2016
@@ -323,7 +323,6 @@ static bool doesModifyCalleeSavedReg(con
return false;
}
-// TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
// Returns true if an instruction can be promoted to .new predicate or
// new-value store.
bool HexagonPacketizerList::isNewifiable(const MachineInstr &MI,
@@ -333,7 +332,7 @@ bool HexagonPacketizerList::isNewifiable
if (NewRC == &Hexagon::PredRegsRegClass)
if (HII->isV60VectorInstruction(MI) && MI.mayStore())
return false;
- return HII->isCondInst(MI) || MI.isReturn() || HII->mayBeNewStore(MI);
+ return HII->isCondInst(MI) || HII->isJumpR(MI) || HII->mayBeNewStore(MI);
}
// Promote an instructiont to its .cur form.
@@ -798,10 +797,8 @@ bool HexagonPacketizerList::canPromoteTo
return false;
// predicate .new
- // bug 5670: until that is fixed
- // TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
if (RC == &Hexagon::PredRegsRegClass)
- if (HII->isCondInst(MI) || MI.isReturn())
+ if (HII->isCondInst(MI) || HII->isJumpR(MI))
return HII->predCanBeUsedAsDotNew(PI, DepReg);
if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
@@ -1291,7 +1288,7 @@ bool HexagonPacketizerList::isLegalToPac
RC = HRI->getMinimalPhysRegClass(DepReg);
}
- if (I.isCall() || I.isReturn() || HII->isTailCall(I)) {
+ if (I.isCall() || HII->isJumpR(I) || HII->isTailCall(I)) {
if (!isRegDependence(DepType))
continue;
if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp?rev=279241&r1=279240&r2=279241&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp Fri Aug 19 09:04:45 2016
@@ -262,25 +262,19 @@ unsigned HexagonMCInstrInfo::getDuplexCa
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
- case Hexagon::PS_jmpret:
// jumpr r31
// Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
DstReg = MCI.getOperand(0).getReg();
- if (Hexagon::R31 == DstReg) {
+ if (Hexagon::R31 == DstReg)
return HexagonII::HSIG_L2;
- }
break;
case Hexagon::J2_jumprt:
case Hexagon::J2_jumprf:
case Hexagon::J2_jumprtnew:
case Hexagon::J2_jumprfnew:
- case Hexagon::PS_jmprett:
- case Hexagon::PS_jmpretf:
- case Hexagon::PS_jmprettnew:
- case Hexagon::PS_jmpretfnew:
- case Hexagon::PS_jmprettnewpt:
- case Hexagon::PS_jmpretfnewpt:
+ case Hexagon::J2_jumprtnewpt:
+ case Hexagon::J2_jumprfnewpt:
DstReg = MCI.getOperand(1).getReg();
SrcReg = MCI.getOperand(0).getReg();
// [if ([!]p0[.new])] jumpr r31
@@ -811,25 +805,20 @@ MCInst HexagonMCInstrInfo::deriveSubInst
break; // none SUBInst deallocframe
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
- case Hexagon::PS_jmpret:
Result.setOpcode(Hexagon::V4_SL2_jumpr31);
break; // none SUBInst jumpr r31
case Hexagon::J2_jumprf:
- case Hexagon::PS_jmpretf:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_f);
break; // none SUBInst if (!p0) jumpr r31
case Hexagon::J2_jumprfnew:
- case Hexagon::PS_jmpretfnewpt:
- case Hexagon::PS_jmpretfnew:
+ case Hexagon::J2_jumprfnewpt:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_fnew);
break; // none SUBInst if (!p0.new) jumpr:nt r31
case Hexagon::J2_jumprt:
- case Hexagon::PS_jmprett:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_t);
break; // none SUBInst if (p0) jumpr r31
case Hexagon::J2_jumprtnew:
- case Hexagon::PS_jmprettnewpt:
- case Hexagon::PS_jmprettnew:
+ case Hexagon::J2_jumprtnewpt:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_tnew);
break; // none SUBInst if (p0.new) jumpr:nt r31
case Hexagon::L2_loadrb_io:
Modified: llvm/trunk/test/CodeGen/Hexagon/block-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/block-addr.ll?rev=279241&r1=279240&r2=279241&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/block-addr.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/block-addr.ll Fri Aug 19 09:04:45 2016
@@ -1,9 +1,8 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; Allow combine(..##JTI..):
-; CHECK: r{{[0-9]+}}{{.*}} = {{.*}}#.LJTI
-; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
-; CHECK: jumpr:nt r{{[0-9]+}}
+; CHECK: .LJTI
+; CHECK-DAG: r[[REG:[0-9]+]] = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
+; CHECK-DAG: jumpr:nt r[[REG]]
define void @main() #0 {
entry:
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