[llvm] r279080 - [GlobalISel] Add floating-point binary ops.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 18 09:05:06 PDT 2016
Author: ab
Date: Thu Aug 18 11:05:06 2016
New Revision: 279080
URL: http://llvm.org/viewvc/llvm-project?rev=279080&view=rev
Log:
[GlobalISel] Add floating-point binary ops.
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
llvm/trunk/include/llvm/Target/GenericOpcodes.td
llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h?rev=279080&r1=279079&r2=279080&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h Thu Aug 18 11:05:06 2016
@@ -217,6 +217,23 @@ private:
return translateBinaryOp(TargetOpcode::G_ASHR, U);
}
+ bool translateFAdd(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_FADD, U);
+ }
+ bool translateFSub(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_FSUB, U);
+ }
+ bool translateFMul(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_FMUL, U);
+ }
+ bool translateFDiv(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_FDIV, U);
+ }
+ bool translateFRem(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_FREM, U);
+ }
+
+
// Stubs to keep the compiler happy while we implement the rest of the
// translation.
bool translateSwitch(const User &U) { return false; }
@@ -226,11 +243,6 @@ private:
bool translateCleanupRet(const User &U) { return false; }
bool translateCatchRet(const User &U) { return false; }
bool translateCatchSwitch(const User &U) { return false; }
- bool translateFAdd(const User &U) { return false; }
- bool translateFSub(const User &U) { return false; }
- bool translateFMul(const User &U) { return false; }
- bool translateFDiv(const User &U) { return false; }
- bool translateFRem(const User &U) { return false; }
bool translateGetElementPtr(const User &U) { return false; }
bool translateFence(const User &U) { return false; }
bool translateAtomicCmpXchg(const User &U) { return false; }
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=279080&r1=279079&r2=279080&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Thu Aug 18 11:05:06 2016
@@ -200,6 +200,48 @@ def G_ICMP : Instruction {
}
//------------------------------------------------------------------------------
+// Floating Point Binary ops.
+//------------------------------------------------------------------------------
+
+// Generic FP addition.
+def G_FADD : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
+// Generic FP subtraction.
+def G_FSUB : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 0;
+}
+
+// Generic FP multiplication.
+def G_FMUL : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
+// Generic FP division.
+def G_FDIV : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+}
+
+// Generic FP remainder.
+def G_FREM : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+}
+
+//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------
Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=279080&r1=279079&r2=279080&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Thu Aug 18 11:05:06 2016
@@ -262,6 +262,21 @@ HANDLE_TARGET_OPCODE(G_ASHR)
/// Generic integer-base comparison, also applicable to vectors of integers.
HANDLE_TARGET_OPCODE(G_ICMP)
+/// Generic FP addition.
+HANDLE_TARGET_OPCODE(G_FADD)
+
+/// Generic FP subtraction.
+HANDLE_TARGET_OPCODE(G_FSUB)
+
+/// Generic FP multiplication.
+HANDLE_TARGET_OPCODE(G_FMUL)
+
+/// Generic FP division.
+HANDLE_TARGET_OPCODE(G_FDIV)
+
+/// Generic FP remainder.
+HANDLE_TARGET_OPCODE(G_FREM)
+
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=279080&r1=279079&r2=279080&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Thu Aug 18 11:05:06 2016
@@ -541,3 +541,58 @@ define void @int_comparison(i32 %a, i32
store i1 %res, i1* %addr
ret void
}
+
+; CHECK-LABEL: name: test_fadd
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_FADD s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %s0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %s0
+define float @test_fadd(float %arg1, float %arg2) {
+ %res = fadd float %arg1, %arg2
+ ret float %res
+}
+
+; CHECK-LABEL: name: test_fsub
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_FSUB s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %s0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %s0
+define float @test_fsub(float %arg1, float %arg2) {
+ %res = fsub float %arg1, %arg2
+ ret float %res
+}
+
+; CHECK-LABEL: name: test_fmul
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_FMUL s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %s0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %s0
+define float @test_fmul(float %arg1, float %arg2) {
+ %res = fmul float %arg1, %arg2
+ ret float %res
+}
+
+; CHECK-LABEL: name: test_fdiv
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_FDIV s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %s0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %s0
+define float @test_fdiv(float %arg1, float %arg2) {
+ %res = fdiv float %arg1, %arg2
+ ret float %res
+}
+
+; CHECK-LABEL: name: test_frem
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_FREM s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %s0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %s0
+define float @test_frem(float %arg1, float %arg2) {
+ %res = frem float %arg1, %arg2
+ ret float %res
+}
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