[PATCH] D23673: [X86][SSE] Add support for 32-bit element vectors to X86ISD::VZEXT_LOAD

[Simon Pilgrim via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, mkuper, spatel, andreadb.
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RKSimon set the repository for this revision to rL LLVM.

Consecutive load matching (EltsFromConsecutiveLoads) currently uses VZEXT_LOAD (load scalar into lowest element and zero uppers) for vXi64 / vXf64 vectors only.

For vXi32 / vXf32 vectors it instead creates a scalar load, SCALAR_TO_VECTOR and finally VZEXT_MOVL (zero upper vector elements), relying on tablegen patterns to match this into an equivalent of VZEXT_LOAD. 

This patch adds the VZEXT_LOAD patterns for vXi32 / vXf32 vectors directly and updates EltsFromConsecutiveLoads to use this.

This has proven necessary to allow us to easily make VZEXT_MOVL a full member of the target shuffle set - without this change the call to combineShuffle (which is the main caller of EltsFromConsecutiveLoads) tended to recursively recreate VZEXT_MOVL nodes......

Repository:
  rL LLVM

https://reviews.llvm.org/D23673

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrSSE.td

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