[llvm] r279073 - [GlobalISel] Add support for DIV/REM.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 18 08:17:08 PDT 2016
Author: ab
Date: Thu Aug 18 10:17:01 2016
New Revision: 279073
URL: http://llvm.org/viewvc/llvm-project?rev=279073&view=rev
Log:
[GlobalISel] Add support for DIV/REM.
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
llvm/trunk/include/llvm/Target/GenericOpcodes.td
llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h?rev=279073&r1=279072&r2=279073&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h Thu Aug 18 10:17:01 2016
@@ -171,6 +171,20 @@ private:
bool translateXor(const User &U) {
return translateBinaryOp(TargetOpcode::G_XOR, U);
}
+
+ bool translateUDiv(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_UDIV, U);
+ }
+ bool translateSDiv(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_SDIV, U);
+ }
+ bool translateURem(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_UREM, U);
+ }
+ bool translateSRem(const User &U) {
+ return translateBinaryOp(TargetOpcode::G_SREM, U);
+ }
+
bool translateAlloca(const User &U) {
return translateStaticAlloca(cast<AllocaInst>(U));
}
@@ -215,11 +229,7 @@ private:
bool translateFAdd(const User &U) { return false; }
bool translateFSub(const User &U) { return false; }
bool translateFMul(const User &U) { return false; }
- bool translateUDiv(const User &U) { return false; }
- bool translateSDiv(const User &U) { return false; }
bool translateFDiv(const User &U) { return false; }
- bool translateURem(const User &U) { return false; }
- bool translateSRem(const User &U) { return false; }
bool translateFRem(const User &U) { return false; }
bool translateGetElementPtr(const User &U) { return false; }
bool translateFence(const User &U) { return false; }
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=279073&r1=279072&r2=279073&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Thu Aug 18 10:17:01 2016
@@ -107,6 +107,38 @@ def G_MUL : Instruction {
let isCommutable = 1;
}
+// Generic signed division.
+def G_SDIV : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 0;
+}
+
+// Generic unsigned division.
+def G_UDIV : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 0;
+}
+
+// Generic signed remainder.
+def G_SREM : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 0;
+}
+
+// Generic unsigned remainder.
+def G_UREM : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 0;
+}
+
// Generic addition consuming and producing a carry flag.
def G_ADDE : Instruction {
let OutOperandList = (outs unknown:$dst, unknown:$carry_out);
Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=279073&r1=279072&r2=279073&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Thu Aug 18 10:17:01 2016
@@ -173,6 +173,18 @@ HANDLE_TARGET_OPCODE(G_SUB)
// Generic multiply instruction.
HANDLE_TARGET_OPCODE(G_MUL)
+// Generic signed division instruction.
+HANDLE_TARGET_OPCODE(G_SDIV)
+
+// Generic unsigned division instruction.
+HANDLE_TARGET_OPCODE(G_UDIV)
+
+// Generic signed remainder instruction.
+HANDLE_TARGET_OPCODE(G_SREM)
+
+// Generic unsigned remainder instruction.
+HANDLE_TARGET_OPCODE(G_UREM)
+
/// Generic bitwise and instruction.
HANDLE_TARGET_OPCODE(G_AND)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=279073&r1=279072&r2=279073&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Thu Aug 18 10:17:01 2016
@@ -459,6 +459,50 @@ define i32 @test_ashr(i32 %arg1, i32 %ar
ret i32 %res
}
+; CHECK-LABEL: name: test_sdiv
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SDIV s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %w0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %w0
+define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
+ %res = sdiv i32 %arg1, %arg2
+ ret i32 %res
+}
+
+; CHECK-LABEL: name: test_udiv
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_UDIV s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %w0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %w0
+define i32 @test_udiv(i32 %arg1, i32 %arg2) {
+ %res = udiv i32 %arg1, %arg2
+ ret i32 %res
+}
+
+; CHECK-LABEL: name: test_srem
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SREM s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %w0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %w0
+define i32 @test_srem(i32 %arg1, i32 %arg2) {
+ %res = srem i32 %arg1, %arg2
+ ret i32 %res
+}
+
+; CHECK-LABEL: name: test_urem
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_UREM s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %w0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %w0
+define i32 @test_urem(i32 %arg1, i32 %arg2) {
+ %res = urem i32 %arg1, %arg2
+ ret i32 %res
+}
+
; CHECK-LABEL: name: test_constant_null
; CHECK: [[NULL:%[0-9]+]](64) = G_CONSTANT p0 0
; CHECK: %x0 = COPY [[NULL]]
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