[llvm] r278832 - [Hexagon] Standardize next batch of pseudo instructions
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 11:08:40 PDT 2016
Author: kparzysz
Date: Tue Aug 16 13:08:40 2016
New Revision: 278832
URL: http://llvm.org/viewvc/llvm-project?rev=278832&view=rev
Log:
[Hexagon] Standardize next batch of pseudo instructions
ALIGNA PS_aligna
ALLOCA PS_alloca
TFR_FI PS_fi
TFR_FIA PS_fia
TFR_PdFalse PS_false
TFR_PdTrue PS_true
VMULW PS_vmulw
VMULW_ACC PS_vmulw_acc
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Tue Aug 16 13:08:40 2016
@@ -1351,8 +1351,8 @@ bool ConstGeneration::isTfrConst(const M
case Hexagon::A4_combineii:
case Hexagon::A2_tfrsi:
case Hexagon::A2_tfrpi:
- case Hexagon::TFR_PdTrue:
- case Hexagon::TFR_PdFalse:
+ case Hexagon::PS_true:
+ case Hexagon::PS_false:
case Hexagon::CONST32:
case Hexagon::CONST64:
return true;
@@ -1397,9 +1397,9 @@ unsigned ConstGeneration::genTfrConst(co
if (RC == &Hexagon::PredRegsRegClass) {
unsigned Opc;
if (C == 0)
- Opc = Hexagon::TFR_PdFalse;
+ Opc = Hexagon::PS_false;
else if ((C & 0xFF) == 0xFF)
- Opc = Hexagon::TFR_PdTrue;
+ Opc = Hexagon::PS_true;
else
return 0;
BuildMI(B, At, DL, HII.get(Opc), Reg);
@@ -2173,7 +2173,7 @@ bool BitSimplification::simplifyTstbit(M
}
} else if (V.is(0) || V.is(1)) {
unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
- unsigned NewOpc = V.is(0) ? Hexagon::TFR_PdFalse : Hexagon::TFR_PdTrue;
+ unsigned NewOpc = V.is(0) ? Hexagon::PS_false : Hexagon::PS_true;
BuildMI(B, At, DL, HII.get(NewOpc), NewR);
HBS::replaceReg(RD.Reg, NewR, MRI);
return true;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp Tue Aug 16 13:08:40 2016
@@ -260,11 +260,11 @@ bool HexagonEvaluator::evaluate(const Ma
case CONST32:
case CONST64:
return rr0(eIMM(im(1), W0), Outputs);
- case TFR_PdFalse:
+ case PS_false:
return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
- case TFR_PdTrue:
+ case PS_true:
return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
- case TFR_FI: {
+ case PS_fi: {
int FI = op(1).getIndex();
int Off = op(2).getImm();
unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp Tue Aug 16 13:08:40 2016
@@ -1994,11 +1994,11 @@ bool HexagonConstEvaluator::evaluate(con
break;
}
- case Hexagon::TFR_PdTrue:
- case Hexagon::TFR_PdFalse:
+ case Hexagon::PS_true:
+ case Hexagon::PS_false:
{
LatticeCell RC = Outputs.get(DefR.Reg);
- bool NonZero = (Opc == Hexagon::TFR_PdTrue);
+ bool NonZero = (Opc == Hexagon::PS_true);
uint32_t P = NonZero ? ConstantProperties::NonZero
: ConstantProperties::Zero;
RC.add(P);
@@ -2328,8 +2328,8 @@ bool HexagonConstEvaluator::rewrite(Mach
case Hexagon::A2_tfrpi:
case Hexagon::CONST32:
case Hexagon::CONST64:
- case Hexagon::TFR_PdTrue:
- case Hexagon::TFR_PdFalse:
+ case Hexagon::PS_true:
+ case Hexagon::PS_false:
return false;
}
@@ -2874,8 +2874,8 @@ bool HexagonConstEvaluator::rewriteHexCo
if (RC != PredRC)
continue;
const MCInstrDesc *NewD = (Ps & P::Zero) ?
- &HII.get(Hexagon::TFR_PdFalse) :
- &HII.get(Hexagon::TFR_PdTrue);
+ &HII.get(Hexagon::PS_false) :
+ &HII.get(Hexagon::PS_true);
unsigned NewR = MRI->createVirtualRegister(PredRC);
const MachineInstrBuilder &MIB = BuildMI(B, At, DL, *NewD, NewR);
(void)MIB;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Tue Aug 16 13:08:40 2016
@@ -99,20 +99,20 @@
// cated (reserved) register, it needs to be kept live throughout the function
// to be available as the base register for local object accesses.
// Normally, an address of a stack objects is obtained by a pseudo-instruction
-// TFR_FI. To access local objects with the AP register present, a different
-// pseudo-instruction needs to be used: TFR_FIA. The TFR_FIA takes one extra
-// argument compared to TFR_FI: the first input register is the AP register.
+// PS_fi. To access local objects with the AP register present, a different
+// pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
+// argument compared to PS_fi: the first input register is the AP register.
// This keeps the register live between its definition and its uses.
-// The AP register is originally set up using pseudo-instruction ALIGNA:
-// AP = ALIGNA A
+// The AP register is originally set up using pseudo-instruction PS_aligna:
+// AP = PS_aligna A
// where
// A - required stack alignment
// The alignment value must be the maximum of all alignments required by
// any stack object.
-// The dynamic allocation uses a pseudo-instruction ALLOCA:
-// Rd = ALLOCA Rs, A
+// The dynamic allocation uses a pseudo-instruction PS_alloca:
+// Rd = PS_alloca Rs, A
// where
// Rd - address of the allocated space
// Rs - minimum size (the actual allocated can be larger to accommodate
@@ -256,8 +256,8 @@ namespace {
return true;
unsigned Opc = MI->getOpcode();
switch (Opc) {
- case Hexagon::ALLOCA:
- case Hexagon::ALIGNA:
+ case Hexagon::PS_alloca:
+ case Hexagon::PS_aligna:
return true;
default:
break;
@@ -536,7 +536,7 @@ void HexagonFrameLowering::insertPrologu
auto &AdjustRegs = FuncInfo->getAllocaAdjustInsts();
for (auto MI : AdjustRegs) {
- assert((MI->getOpcode() == Hexagon::ALLOCA) && "Expected alloca");
+ assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
expandAlloca(MI, HII, SP, MaxCF);
MI->eraseFromParent();
}
@@ -2322,7 +2322,7 @@ const MachineInstr *HexagonFrameLowering
const MachineFunction &MF) const {
for (auto &B : MF)
for (auto &I : B)
- if (I.getOpcode() == Hexagon::ALIGNA)
+ if (I.getOpcode() == Hexagon::PS_aligna)
return &I;
return nullptr;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Tue Aug 16 13:08:40 2016
@@ -934,22 +934,16 @@ void HexagonDAGToDAGISel::SelectConstant
}
//
-// Map predicate true (encoded as -1 in LLVM) to a XOR.
+// Map boolean values.
//
void HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
- SDLoc dl(N);
if (N->getValueType(0) == MVT::i1) {
- SDNode* Result = 0;
- int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
- if (Val == -1) {
- Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl, MVT::i1);
- } else if (Val == 0) {
- Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1);
- }
- if (Result) {
- ReplaceNode(N, Result);
- return;
- }
+ assert(!(cast<ConstantSDNode>(N)->getZExtValue() >> 1));
+ unsigned Opc = (cast<ConstantSDNode>(N)->getSExtValue() != 0)
+ ? Hexagon::PS_true
+ : Hexagon::PS_false;
+ ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i1));
+ return;
}
SelectCode(N);
@@ -1141,19 +1135,19 @@ void HexagonDAGToDAGISel::SelectFrameInd
SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
SDNode *R = nullptr;
- // Use TFR_FI when:
+ // Use PS_fi when:
// - the object is fixed, or
// - there are no objects with higher-than-default alignment, or
// - there are no dynamically allocated objects.
- // Otherwise, use TFR_FIA.
+ // Otherwise, use PS_fia.
if (FX < 0 || MaxA <= StkA || !MFI.hasVarSizedObjects()) {
- R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
+ R = CurDAG->getMachineNode(Hexagon::PS_fi, DL, MVT::i32, FI, Zero);
} else {
auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
unsigned AR = HMFI.getStackAlignBaseVReg();
SDValue CH = CurDAG->getEntryNode();
SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero };
- R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops);
+ R = CurDAG->getMachineNode(Hexagon::PS_fia, DL, MVT::i32, Ops);
}
ReplaceNode(N, R);
@@ -1388,7 +1382,7 @@ void HexagonDAGToDAGISel::EmitFunctionEn
MachineBasicBlock *EntryBB = &MF->front();
unsigned AR = FuncInfo->CreateReg(MVT::i32);
unsigned MaxA = MFI.getMaxAlignment();
- BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::ALIGNA), AR)
+ BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)
.addImm(MaxA);
MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue Aug 16 13:08:40 2016
@@ -2954,7 +2954,7 @@ HexagonTargetLowering::getPICJumpTableRe
MachineBasicBlock *HexagonTargetLowering::EmitInstrWithCustomInserter(
MachineInstr &MI, MachineBasicBlock *BB) const {
switch (MI.getOpcode()) {
- case Hexagon::ALLOCA: {
+ case Hexagon::PS_alloca: {
MachineFunction *MF = BB->getParent();
auto *FuncInfo = MF->getInfo<HexagonMachineFunctionInfo>();
FuncInfo->addAllocaAdjustInst(&MI);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Aug 16 13:08:40 2016
@@ -1007,7 +1007,7 @@ bool HexagonInstrInfo::expandPostRAPseud
MBB.erase(MBBI);
return true;
}
- case Hexagon::ALIGNA:
+ case Hexagon::PS_aligna:
BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
.addReg(HRI.getFrameRegister())
.addImm(-MI.getOperand(1).getImm());
@@ -1113,7 +1113,7 @@ bool HexagonInstrInfo::expandPostRAPseud
MBB.erase(MI);
return true;
}
- case Hexagon::TFR_PdTrue: {
+ case Hexagon::PS_true: {
unsigned Reg = MI.getOperand(0).getReg();
BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
.addReg(Reg, RegState::Undef)
@@ -1121,7 +1121,7 @@ bool HexagonInstrInfo::expandPostRAPseud
MBB.erase(MI);
return true;
}
- case Hexagon::TFR_PdFalse: {
+ case Hexagon::PS_false: {
unsigned Reg = MI.getOperand(0).getReg();
BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
.addReg(Reg, RegState::Undef)
@@ -1129,7 +1129,7 @@ bool HexagonInstrInfo::expandPostRAPseud
MBB.erase(MI);
return true;
}
- case Hexagon::VMULW: {
+ case Hexagon::PS_vmulw: {
// Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Src1Reg = MI.getOperand(1).getReg();
@@ -1153,7 +1153,7 @@ bool HexagonInstrInfo::expandPostRAPseud
MRI.clearKillFlags(Src2SubLo);
return true;
}
- case Hexagon::VMULW_ACC: {
+ case Hexagon::PS_vmulw_acc: {
// Expand 64-bit vector multiply with addition into 2 scalar multiplies.
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Src1Reg = MI.getOperand(1).getReg();
@@ -2063,8 +2063,9 @@ bool HexagonInstrInfo::isExtendable(cons
// TODO: This is largely obsolete now. Will need to be removed
// in consecutive patches.
switch (MI.getOpcode()) {
- // TFR_FI Remains a special case.
- case Hexagon::TFR_FI:
+ // PS_fi and PS_fia remain special cases.
+ case Hexagon::PS_fi:
+ case Hexagon::PS_fia:
return true;
default:
return false;
@@ -2762,8 +2763,8 @@ bool HexagonInstrInfo::isValidOffset(uns
case Hexagon::LDriw_mod:
return true;
- case Hexagon::TFR_FI:
- case Hexagon::TFR_FIA:
+ case Hexagon::PS_fi:
+ case Hexagon::PS_fia:
case Hexagon::INLINEASM:
return true;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Aug 16 13:08:40 2016
@@ -4517,14 +4517,14 @@ def Y2_barrier : SYSInst<(outs), (ins),
//
let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
- def TFR_FI : ALU32_ri<(outs IntRegs:$Rd),
- (ins IntRegs:$fi, s32Imm:$off), "">;
- def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
+ def PS_fi : ALU32_ri<(outs IntRegs:$Rd),
+ (ins IntRegs:$fi, s32Imm:$off), "">;
+ def PS_fia : ALU32_ri<(outs IntRegs:$Rd),
+ (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
}
-def: Pat<(i32 (orisadd (i32 AddrFI:$Rs), s32ImmPred:$off)),
- (i32 (TFR_FI (i32 AddrFI:$Rs), s32ImmPred:$off))>;
+def: Pat<(orisadd (i32 AddrFI:$Rs), s32ImmPred:$off),
+ (PS_fi (i32 AddrFI:$Rs), s32ImmPred:$off)>;
//===----------------------------------------------------------------------===//
// CRUSER - Type.
@@ -4778,13 +4778,13 @@ def: Pat<(HexagonCONST32 bbl:$label),
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
isCodeGenOnly = 1 in
-def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "",
- [(set (i1 PredRegs:$dst), 1)]>;
+def PS_true : SInst<(outs PredRegs:$dst), (ins), "",
+ [(set (i1 PredRegs:$dst), 1)]>;
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
isCodeGenOnly = 1 in
-def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "",
- [(set (i1 PredRegs:$dst), 0)]>;
+def PS_false : SInst<(outs PredRegs:$dst), (ins), "",
+ [(set (i1 PredRegs:$dst), 0)]>;
// Pseudo instructions.
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
@@ -5073,13 +5073,13 @@ def HexagonALLOCA : SDNode<"HexagonISD::
// in MachineFunctionInfo.
let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1,
usesCustomInserter = 1 in
-def ALLOCA: ALU32Inst<(outs IntRegs:$Rd),
+def PS_alloca: ALU32Inst<(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u32Imm:$A), "",
[(set (i32 IntRegs:$Rd),
(HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>;
let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
-def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
+def PS_aligna : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td Tue Aug 16 13:08:40 2016
@@ -238,15 +238,13 @@ def: vcmp_vi1_pat<A2_vcmphgtu, setugt, V
// scalar MPYI instructions.
// This is expanded by ExpandPostRAPseudos.
let isPseudo = 1 in
-def VMULW : PseudoM<(outs DoubleRegs:$Rd),
- (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
- ".error \"Should never try to emit VMULW\"",
+def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
+ (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "",
[(set V2I32:$Rd, (mul V2I32:$Rs, V2I32:$Rt))]>;
let isPseudo = 1 in
-def VMULW_ACC : PseudoM<(outs DoubleRegs:$Rd),
- (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt),
- ".error \"Should never try to emit VMULW_ACC\"",
+def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
+ (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "",
[(set V2I32:$Rd, (add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)))],
"$Rd = $Rx">;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=278832&r1=278831&r2=278832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Tue Aug 16 13:08:40 2016
@@ -180,12 +180,12 @@ void HexagonRegisterInfo::eliminateFrame
unsigned Opc = MI.getOpcode();
switch (Opc) {
- case Hexagon::TFR_FIA:
+ case Hexagon::PS_fia:
MI.setDesc(HII.get(Hexagon::A2_addi));
MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
MI.RemoveOperand(FIOp+1);
return;
- case Hexagon::TFR_FI:
+ case Hexagon::PS_fi:
// Set up the instruction for updating below.
MI.setDesc(HII.get(Hexagon::A2_addi));
break;
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