[PATCH] D23456: [Sparc] Leon Errata Fix Passes
Daniel Cederman via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 13 01:25:35 PDT 2016
dcederman added inline comments.
================
Comment at: lib/Target/Sparc/LeonFeatures.td:14-31
@@ -14,53 +13,20 @@
//===----------------------------------------------------------------------===//
-// UMAC and SMAC support for LEON3 and LEON4 processors.
+// CASA Support differs between LEON3-FT GR712RC and LEON3-FT UT699
+// We need to have the option to switch this on and off.
//===----------------------------------------------------------------------===//
-//support to casa instruction; for leon3 subtarget only
-def UMACSMACSupport : SubtargetFeature<
- "hasumacsmac",
- "HasUmacSmac",
- "true",
- "Enable UMAC and SMAC for LEON3 and LEON4 processors"
->;
-
+// support to casa instruction; for leon3 subtarget only
+def LeonCASA : SubtargetFeature<
+ "hasleoncasa", "HasLeonCasa", "true",
+ "Enable CASA instruction for LEON3 and LEON4 processors">;
//===----------------------------------------------------------------------===//
-// CASA Support differs between LEON3-FT GR712RC and LEON3-FT UT699
-// We need to have the option to switch this on and off.
+// UMAC and SMAC support for LEON3 and LEON4 processors.
//===----------------------------------------------------------------------===//
-//support to casa instruction; for leon3 subtarget only
-def LeonCASA : SubtargetFeature<
- "hasleoncasa",
- "HasLeonCasa",
- "true",
- "Enable CASA instruction for LEON3 and LEON4 processors"
->;
-
-def InsertNOPLoad: SubtargetFeature<
- "insertnopload",
- "InsertNOPLoad",
- "true",
- "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction"
->;
-
-def FixFSMULD : SubtargetFeature<
- "fixfsmuld",
- "FixFSMULD",
- "true",
- "LEON erratum fix: Do not use FSMULD"
->;
-
-def ReplaceFMULS : SubtargetFeature<
- "replacefmuls",
- "ReplaceFMULS",
- "true",
- "LEON erratum fix: Replace FMULS instruction with FMULD and relevant conversion instructions"
->;
-
-def FixAllFDIVSQRT : SubtargetFeature<
- "fixallfdivsqrt",
- "FixAllFDIVSQRT",
- "true",
- "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
->;
+// support to casa instruction; for leon3 subtarget only
+def UMACSMACSupport
+ : SubtargetFeature<"hasumacsmac", "HasUmacSmac", "true",
+ "Enable UMAC and SMAC for LEON3 and LEON4 processors">;
+
+//===----------------------------------------------------------------------===//
----------------
The above changes are not related to the errata fixes. You should move them to a separate patch.
================
Comment at: lib/Target/Sparc/LeonPasses.cpp:373-410
@@ +372,40 @@
+
+//*****************************************************************************
+//**** FixCALL pass
+//*****************************************************************************
+// This pass restricts the size of the immediate operand of the CALL
+// instruction, which can cause problems on some earlier versions of the LEON
+// processor, which can interpret some of the call address bits incorrectly.
+//
+char FixCALL::ID = 0;
+
+FixCALL::FixCALL(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
+
+bool FixCALL::runOnMachineFunction(MachineFunction &MF) {
+ bool Modified = false;
+
+ for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
+ MachineBasicBlock &MBB = *MFI;
+ for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
+ MachineInstr &MI = *MBBI;
+
+ unsigned Opcode = MI.getOpcode();
+ if (Opcode == SP::CALL || Opcode == SP::CALLrr) {
+ unsigned NumOperands = MI.getNumOperands();
+ for (unsigned OperandIndex = 0; OperandIndex < NumOperands;
+ OperandIndex++) {
+ MachineOperand &MO = MI.getOperand(OperandIndex);
+ if (MO.isImm()) {
+ int64_t Value = MO.getImm();
+ MO.setImm(Value & 0x000fffffL);
+ Modified = true;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ return Modified;
+}
+
----------------
Truncating the immediate will cause the call to go to the wrong address, so this is not a valid fix.
The errata also only applies to the CALL instruction, not CALLrr or CALLri, which are pseudo instructions that map to JMPL.
You instead need to check for CALL instructions with bit 24 = 1 and bit 21 = 0, or any CALL instruction where the address is resolved in the linker stage, and build a new call using SETHI and CALLri instead of CALL.
================
Comment at: lib/Target/Sparc/LeonPasses.cpp:417-418
@@ +416,4 @@
+// instructions that exists on some earlier LEON processors. Where these
+// instructions are detected, they are replaced by a sequence that will
+// explicitly write the overflow bit flag if this is required.
+//
----------------
Is it required? I cannot see that those instruction are generated by the compiler or any overflow bit checks.
================
Comment at: lib/Target/Sparc/LeonPasses.cpp:470-475
@@ +469,8 @@
+
+ // use the WRPSR (Write Processor State Register) instruction to set the
+ // zeo flag to 1
+ // create wr %g0, 1, %psr
+ BuildMI(MBB, NextMBBI, DL, TII.get(SP::WRPSRri))
+ .addReg(SP::G0)
+ .addImm(1);
+
----------------
This does not do what you want it to do. Please try it on hardware.
================
Comment at: lib/Target/Sparc/LeonPasses.cpp:516
@@ +515,3 @@
+ unsigned Opcode = MI.getOpcode();
+ if (Opcode == SP::LDDFri || Opcode == SP::LDDFrr) {
+ MachineBasicBlock::iterator NMBBI = std::next(MBBI);
----------------
The errata is for single-word floats so you should change that to LDFri and LDFrr.
================
Comment at: lib/Target/Sparc/Sparc.td:24
@@ -23,4 +23,3 @@
def FeatureV9
- : SubtargetFeature<"v9", "IsV9", "true",
- "Enable SPARC-V9 instructions">;
+ : SubtargetFeature<"v9", "IsV9", "true", "Enable SPARC-V9 instructions">;
def FeatureV8Deprecated
----------------
There are several unrelated changes in this file. Please move them to a separate patch.
================
Comment at: lib/Target/Sparc/SparcISelLowering.cpp:27
@@ -26,3 +26,3 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
----------------
Same with this file. Move the unrelated changes to a separate patch.
================
Comment at: test/CodeGen/SPARC/LeonConvertDoubleFPToSingleFPInstrUT.ll:1-4
@@ +1,5 @@
+; RUN: llc < %s -O0 -march=sparc -mcpu=leon2 -enable-leon-float-optimizer | FileCheck %s
+; RUN: llc < %s -O0 -march=sparc -mcpu=leon3 -enable-leon-float-optimizer | FileCheck %s
+; RUN: llc < %s -O0 -march=sparc -mcpu=leon4 -enable-leon-float-optimizer | FileCheck %s
+; RUN: llc < %s -O0 -march=sparc -mcpu=at697e -enable-leon-float-optimizer | FileCheck %s
+; RUN: llc < %s -O0 -march=sparc -mcpu=at697f -enable-leon-float-optimizer | FileCheck %s
----------------
Unrelated.
Repository:
rL LLVM
https://reviews.llvm.org/D23456
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