[PATCH] D23446: [X86] Enable setcc to srl(ctlz) transformation on btver2 architectures.

[pierre gousseau via llvm-commits]

pgousseau created this revision.
pgousseau added reviewers: qcolombet, andreadb, RKSimon, spatel.
pgousseau added a subscriber: llvm-commits.
Herald added a subscriber: nemanjai.

Following the discussion on D22038, this change enables the setcc to srl(ctlz) transformation on the btver2 architecture.
This optimisation is beneficial on Jaguar architecture only, where the lzcnt has a good reciprocal throughput.
Other architectures such as Intel's Haswell/Broadwell or AMD's Bulldozer/PileDriver do not benefit from it.
For this reason the change also add a "HasFastLZCNT" feature which gets enabled for Jaguar.

This patch requires D23445

https://reviews.llvm.org/D23446

Files:
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/lzcnt-zext-cmp.ll

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