[PATCH] D23365: [AArch64] Re-factor code shared by AArch64LoadStoreOpt and AArch64InstrInfo.

[Geoff Berry via llvm-commits]

gberry added inline comments.

================
Comment at: lib/Target/AArch64/AArch64InstrInfo.cpp:1606
@@ -1605,3 +1605,1 @@
     const TargetRegisterInfo *TRI) const {
-  switch (LdSt.getOpcode()) {
-  default:
----------------
mcrosier wrote:
> The getMemOpBaseRegImmOfs() function is used to control lots of moving parts such as the clustering of loads and stores in the MI scheduler, scheduling in the swing modulo scheduler, and implicit null checks in machine sink, for example.  Removing this switch and unconditionally calling getMemOpBaseRegImmOfsWidth will return true for many more opcodes (e.g., paired instructions, paired instructions with non-temporal hints, byte and halfword loads/stores).
> 
> I just wanted to point this out and confirm that you've done a fair amount of due diligence to make sure this really is a NFC.
Yes, you are right, this change isn't quite NFC.  I've updated the description to reflect this.


https://reviews.llvm.org/D23365