[PATCH] D23379: BranchRelaxation: Fix handling of blocks with multiple conditional branches

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: t.p.northover.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: aemerson.

Looping over all terminators exposed AArch64 tests hitting
an assert from analyzeBranch failing. I believe these cases
were miscompiled before.
    
    e.g.
      fcmp s0, s1
      b.ne LBB0_1
      b.vc LBB0_2
      b LBB0_2
    LBB0_1:
      ; Large block
    LBB0_2:
     ; ...
    
Both of the individual conditional branches need to
be expanded, since neither can reach the final block.
    
Split the original block into ones which analyzeBranch
will be able to understand.


https://reviews.llvm.org/D23379

Files:
  lib/CodeGen/BranchRelaxation.cpp
  test/CodeGen/AArch64/branch-relax-bcc.ll

Index: test/CodeGen/AArch64/branch-relax-bcc.ll
===================================================================
--- test/CodeGen/AArch64/branch-relax-bcc.ll
+++ test/CodeGen/AArch64/branch-relax-bcc.ll
@@ -1,16 +1,22 @@
 ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s
 
 ; CHECK-LABEL: invert_bcc:
-; CHECK:       fcmp s0, s1
-; CHECK-NEXT:  b.ne [[BB1:LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT:  b.vs [[BB2:LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT:  b [[BB2]]
+; CHECK:      fcmp s0, s1
+; CHECK-NEXT: b.eq [[JUMP_BB1:LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT: b [[JUMP_BB2:LBB[0-9]+_[0-9]+]]
 
-; CHECK: [[BB1]]:
+; CHECK-NEXT: [[JUMP_BB1]]:
+; CHECK-NEXT: b [[BB1:LBB[0-9]+_[0-9]+]]
+
+; CHECK-NEXT: [[JUMP_BB2]]:
+; CHECK-NEXT: b.vc [[BB2:LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT: b [[BB1]]
+
+; CHECK: [[BB2]]: ; %bb2
 ; CHECK: mov w{{[0-9]+}}, #9
 ; CHECK: ret
 
-; CHECK: [[BB2]]:
+; CHECK: [[BB1]]: ; %bb1
 ; CHECK: mov w{{[0-9]+}}, #42
 ; CHECK: ret
 
Index: lib/CodeGen/BranchRelaxation.cpp
===================================================================
--- lib/CodeGen/BranchRelaxation.cpp
+++ lib/CodeGen/BranchRelaxation.cpp
@@ -445,8 +445,24 @@
       if (MI.isConditionalBranch()) {
         if (MachineBasicBlock *DestBB = TII->getBranchDestBlock(MI)) {
           if (!isBlockInRange(MI, *DestBB)) {
-            fixupConditionalBranch(MI);
-            ++NumConditionalRelaxed;
+            if (Next != MBB.end() && Next->isConditionalBranch()) {
+              // If there are multiple conditional branches, this isn't an
+              // analyzable block. Split later terminators into a new block so
+              // each one will be analyzable.
+
+              MachineBasicBlock *NewBB = splitBlockBeforeInstr(*Next);
+              NewBB->transferSuccessors(&MBB);
+              MBB.addSuccessor(NewBB);
+              MBB.addSuccessor(DestBB);
+
+              // Cleanup potential unconditional branch to successor block.
+              NewBB->updateTerminator();
+              MBB.updateTerminator();
+            } else {
+              fixupConditionalBranch(MI);
+              ++NumConditionalRelaxed;
+            }
+
             Changed = true;
 
             // This may have modified all of the terminators, so start over.


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