[PATCH] D23367: [SystemZ] Use valid base/index registers for memory constraints

[Zhan Jun Liau via llvm-commits]

zhanjunl created this revision.
zhanjunl added a reviewer: uweigand.
zhanjunl added a subscriber: llvm-commits.

Inline asm memory constraints can have the base or index register be assigned to %r0 right now.
Make sure that we assign only ADDR64 registers to the base and index.

https://reviews.llvm.org/D23367

Files:
  lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
  test/CodeGen/SystemZ/asm-02.ll

Index: test/CodeGen/SystemZ/asm-02.ll
===================================================================
--- test/CodeGen/SystemZ/asm-02.ll
+++ test/CodeGen/SystemZ/asm-02.ll
@@ -74,8 +74,8 @@
 ; Check that LAY is used if there is an index but the displacement is too large
 define void @f7(i64 %base, i64 %index) {
 ; CHECK-LABEL: f7:
-; CHECK: lay %r0, 4096(%r3,%r2)
-; CHECK: blah 0(%r0)
+; CHECK: lay %r1, 4096(%r3,%r2)
+; CHECK: blah 0(%r1)
 ; CHECK: br %r14
   %add = add i64 %base, 4096
   %addi = add i64 %add, %index
Index: lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
===================================================================
--- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -1375,6 +1375,29 @@
   }
 
   if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) {
+    const TargetRegisterClass *TRC =
+      Subtarget->getRegisterInfo()->getPointerRegClass(*MF);
+    SDLoc DL(Base);
+    SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32);
+
+    // Make sure that the base address doesn't go into %r0.
+    // If it's a TargetFrameIndex or a fixed register, we shouldn't do anything.
+    if (Base.getOpcode() != ISD::TargetFrameIndex &&
+        Base.getOpcode() != ISD::Register) {
+      Base =
+        SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
+                                       DL, Base.getValueType(),
+                                       Base, RC), 0);
+    }
+
+    // Make sure that the index register isn't assigned to %r0 either.
+    if (Index.getOpcode() != ISD::Register) {
+      Index =
+        SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
+                                       DL, Index.getValueType(),
+                                       Index, RC), 0);
+    }
+
     OutOps.push_back(Base);
     OutOps.push_back(Disp);
     OutOps.push_back(Index);


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